Summary and Suggestions for Future Research

Abstract

The deep submicron technologies are challenging test in a number of areas. The fabrication cost of transistors continues to reduce while the cost of testing is not scaling. Geometries shrink while the defect sizes do not shrink in proportion. The increase in wiring levels demands new fault models. Many of the design problems due to deep submicron technology which include distributed delay variations, crosstalk-induced delay and logic errors, excessive voltage drop, and swing on power nets have become test problems as well. The problem of test generation due to this deep submicron parametric variation belongs to the class of non-deterministic polynomial (NP) complete problems, and it is becoming more complex as complexity of integrated circuit increases. Hence, to ensure the proper functionality and reliability of VLSI circuits, complicated design and effective test methods are the requirements. Efforts are required to analyze and to develop test methods for crosstalk, delay, and power dissipation in current technology moving into an ultra-DSM and nanotechnology. Of the various noise sources, signal integrity problems due to increasing cross-coupling will have a significant adverse effect on the proper functioning and performance of VLSI systems. The number of design and analysis tools is available in the literature to minimize the effects of crosstalk. However, it is not possible to predict all the manufacturing defects and process variations in advance that may increase the cross-coupling effects. Hence, there is a need for testing manufacturing anomalies to screen out defective parts. The development of efficient test generation methodologies for crosstalk delay faults has been an active area of research. A survey of related literature revealed that there is a considerable scope for the development of algorithm for test generation and simulation of crosstalk delay faults in combinational and sequential circuits.