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Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?

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Abstract

Empirical observation shows that practically encountered instances of combinational ATPG are efficiently solvable. However, it has been known for more than two decades that ATPG is an NP-complete problem (Ibarra and Sahni, IEEE Transactions on Computers, Vol. C-24, No. 3, pp. 242–249, March 1975). This work is one of the first attempts to reconcile these seemingly disparate results. We introduce the concept of cut-width of a circuit and characterize the complexity of ATPG in terms of this property. We introduce the class of log-bounded width circuits and prove that combinational ATPG is efficiently solvable on members of this class. The class of of log-bounded width circuits is shown to strictly subsume the class of k-bounded circuits introduced by Fujiwara (International Symposium on Fault-Tolerant Computing, June 1988, pp. 64–69). We provide empirical evidence which indicates that an interestingly large class of practical circuits is expected to have log-bounded width, which ensures efficient solution of ATPG on them.

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References

  1. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.

    Google Scholar 

  2. D. Brand, “Verification of Large Synthesized Designs,” in Proc. IEEE International Conference on Computer Aided Design, 1993, pp. 534-537.

  3. R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, “MIS: A Multiple-Level Logic Optimization System,” IEEE Transactions on CAD/ICAS, Vol. CAD-6, pp. 1062-1082, Nov. 1987.

  4. C.L. Berman, “Circuit Width, Register Allocation and Ordered Binary Decision Diagrams,” IEEE Transactions on Computer-Aided Design, Vol. 10, pp. 1059-1066, Aug. 1991.

  5. E. Boros, Y. Crama, and P.L. Hammer, “Polynomial-Time Inference of All Valid Implications for Horn and Related Formulae,” Ann. Math Art. Intell., Vol. 1, pp. 21-32, 1990.

    Google Scholar 

  6. E. Boros, Y. Crama, P.L. Hammer, and M. Saks, “A Complexity Index for Satisfiability Problems,” SIAM Journal of Computing, Vol. 23, pp. 45-49, Feb. 1994.

  7. F. Brglez and H. Fujiwara, “A Neural Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” in Proc. International Symposium on Circuits and Systems, June 1985.

  8. K.-T. Cheng and L.A. Entrena, “Combinational and Sequential Logic Optimization by Redundancy Addition and Removal,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, pp. 909-916, July 1995.

    Google Scholar 

  9. P. Chong, M.R. Prasad, K. Keutzer, and R.K. Brayton, “Why is ATPG Easy?,” Technical Report, ERL, University of California, Berkeley, 1998.

    Google Scholar 

  10. O. Coudert, “Exact Coloring of Real-Life Graphs is Easy,” in Proceedings of the 34th DAC, June 1997, pp. 121-126.

  11. S. Devadas, H.-K.T. Ma, and A. Sangiovanni-Vincentelli, “Logic Verification, Testing and Their Relationship to Logic Synthesis,” Testing and Diagnosis of VLSI and ULSI, Kluwer Academic Publishers, Dordrecht, 1988, pp. 181-246.

    Google Scholar 

  12. H. Fujiwara, “Computational Complexity of Controllability/Observability Problems for Combinaitonal Circuits,” in Proc. International Symposium on Fault-Tolerant Computing, June 1988, pp. 64-69.

  13. M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, New York: W.H. Freeman and Company, 1979.

    Google Scholar 

  14. D. Ghosh and F. Brglez, “Equivalence Classes of Circuit Mutants for Experimental Design,” in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI, 1999, pp. 432-435.

  15. J. Gu, P.W. Purdom, J. Franco, and B.W. Wah, “Algorithms for the Satisfiability (SAT) Problem: A Survery,” DIMACS Series in Discrete Mathematics and Computer Science, Vol. 35, pp. 19-151, 1997.

    Google Scholar 

  16. D.S. Hochbaum (ed.), Approximation Algorithms for NP-Hard Problems, Boston, MA: PWS Publishing Company, 1997.

    Google Scholar 

  17. M. Hutton, J.P. Grossman, J. Rose, and D. Corneil, “Characterization and Paramterized Generation of Synthetic Combinational Benchmark Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, pp. 985-996, Oct. 1998.

    Google Scholar 

  18. O.H. Ibarra and S.K. Sahni, “Polynomially Complete Fault Detection Problems,” IEEE Transactions on Computers, Vol. C-24,No. 3, pp. 242-249, March 1975.

    Google Scholar 

  19. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “Multilevel Hypergraph Partitioning: Applications in VLSI Domain,” IEEE Transactions on VLSI Systems, Vol. 7, pp. 69-79, March 1999.

  20. A. Kuehlmann, A. Srinivasan, and D.P. LaPotin, “Verity—A Formal Verification Program for Custom CMOS Circuits,” IBM Journal of Research and Development, Vol. 39, pp. 149-165, 1995.

    Google Scholar 

  21. T. Larrabee, “Test Pattern Generation Using Boolean Satisfiability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, pp. 4-15, Jan. 1992.

    Google Scholar 

  22. K.L. McMillan, Symbolic Model Checking: An Approach to the State Explosion Problem, Ph.D. Thesis, School of Computer Science, Carnegie Mellon University, 1992.

  23. S.L. Meyer, Data Analysis For Scientists and Engineers, Wiley and Sons, 1975.

  24. P.W. Purdom and C.A. Brown, “Polynomial-Average-Time Satisfiability Problems,” Information Sciences, Vol. 41, pp. 23-42, 1987.

    Google Scholar 

  25. J.A. Rice, Mathematical Statistics and Data Analysis, 2nd edn; Belmont, CA: International Thompson Publishing, 1995.

    Google Scholar 

  26. Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, and Alberto Sangiovanni-Vincentell, “SIS: A System for Sequential Circuit Synthesis,” Technical Report UCB/ERL M92/41, ERL, College of Engineering, University of California, Berkeley, May 1998.

    Google Scholar 

  27. J.P.M.-Silva and K. Sakallah, “GRASP: A Search Algorithm for Propositional Satisfiability,” IEEE Transactions on Computers, Vol. 48, pp. 506-521, May 1999.

    Google Scholar 

  28. P. Stephan, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Combinational Test Generation Using Satisfiability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, pp. 1167-1176, Sept. 1996.

    Google Scholar 

  29. T.W. Williams and K. Parker, “Testing Logic Networks and Designing for Testability,” Computer, pp. 9-21, Oct. 1979.

  30. S. Yang, “Logic Synthesis and Optimization Benchmarks User Guide, Version 3.0,” Technical Report, Microelectronics Center of North Carolina, 1991.

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Authors and Affiliations

  1. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 94720, USA

    Mukul R. Prasad, Philip Chong & Kurt Keutzer

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  1. Mukul R. Prasad
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  2. Philip Chong
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  3. Kurt Keutzer
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Prasad, M.R., Chong, P. & Keutzer, K. Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?. Journal of Electronic Testing 17, 509–527 (2001). https://doi.org/10.1023/A:1012820722053

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