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Correlation Bounds and #SAT Algorithms for Small Linear-Size Circuits

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Computing and Combinatorics (COCOON 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9198))

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Abstract

We revisit the gate elimination method, generalize it to prove correlation bounds of boolean circuits with Parity, and also derive deterministic #SAT algorithms for small linear-size circuits. In particular, we prove that, for boolean circuits of size \(3n - n^{0.51}\), the correlation with Parity is at most \(2^{-n^{\varOmega (1)}}\), and there is a #SAT algorithm running in time \(2^{n-n^{\varOmega (1)}}\); for circuit size 2.99n, the correlation with Parity is at most \(2^{-{\varOmega (n)}}\), and there is a #SAT algorithm running in time \(2^{n-{\varOmega (n)}}\). Similar correlation bounds and algorithms are also proved for circuits of size almost 2.5n over the full binary basis \(B_2\).

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Author information

Authors and Affiliations

  1. School of Informatics, University of Edinburgh, Edinburgh, UK

    Ruiwen Chen

  2. School of Computing Science, Simon Fraser University, Burnaby, BC, Canada

    Valentine Kabanets

Authors
  1. Ruiwen Chen
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  2. Valentine Kabanets
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Correspondence to Ruiwen Chen .

Editor information

Editors and Affiliations

  1. Beijing University of Technology, Beijing, China

    Dachuan Xu

  2. University of New Brunswick, Fredericton, Canada

    Donglei Du

  3. University of Texas at Dallas, Richardson, USA

    Dingzhu Du

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Chen, R., Kabanets, V. (2015). Correlation Bounds and #SAT Algorithms for Small Linear-Size Circuits. In: Xu, D., Du, D., Du, D. (eds) Computing and Combinatorics. COCOON 2015. Lecture Notes in Computer Science(), vol 9198. Springer, Cham. https://doi.org/10.1007/978-3-319-21398-9_17

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  • DOI: https://doi.org/10.1007/978-3-319-21398-9_17

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-21397-2

  • Online ISBN: 978-3-319-21398-9

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