Abstract
This paper presents a new simple and straightforward method for designing Completely Testable Embedded (CTE) parity trees, and Self-Testing Embedded (STE) two-rail checkers. In the design of CTE parity trees the two inputs XOR gate has been used as the building block. In the case of STE two-rail checkers with n input pairs the building block is the two-rail checker with 2 input pairs. During normal, fault free, operation each XOR gate receives all possible input vectors, while each two-rail checker with 2 input pairs receives all possible code input vectors. The great advantage of the proposed method is that it is the only one that gives in a simple and straightforward way an optimal CTE/STE tree realization with respect to the hardware (number of blocks) and the speed (number of block levels). Designing the two input two-rail checker as proposed by Lo in IEEE J. of Solid-State Circuits, 1993, we get optimal STE two-rail checkers taking into account realistic faults.
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Nikolos, D. Self-Testing Embedded Two-Rail Checkers. Journal of Electronic Testing 12, 69–79 (1998). https://doi.org/10.1023/A:1008281822966
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DOI: https://doi.org/10.1023/A:1008281822966