Abstract
We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Piscataway, NJ: IEEE Press, 1990.
A. Balakrishnan and S.T. Chakradhar, “Sequential Circuits with Combinational Test Generation Complexity,” in Proc. Intl. Conf. on VLSI Design, 1996, pp. 111–117.
J.E. Chen, C.L. Lee, and W.Z. Shen, “Single-Fault Fault-Collapsing Analysis in Sequential Logic Circuits,” IEEE Trans. on Computer-Aided Design, vol. 10, pp. 1559–1568, Dec. 1991.
J.E. Chen, C.L. Lee, W.Z. Shen, and B. Chen, “Fanout Fault Analysis for Digital Logic Circuits,” in Proc. Asian Test Symposium, 1995, pp. 33–37.
H. Fujiwara, Logic Testing and Design for Testability, Cambridge, MA: The MIT Press, 1985.
H. Fujiwara, “A New Class of Sequential Circuits with Combinational Test Generation Complexity,” IEEE Trans. on Computers, vol. 49, pp. 895–905, Sept. 2000.
R. Gupta and M.A. Breuer, “Partial Scan Design of Register-Transfer Level Circuits,” Journal of Electronic Testing: Theory and Applications, vol. 7, pp. 25–46, 1995.
R. Gupta, R. Gupta, and M. Breuer, “The BALLAST Methodology for Structured Partial Scan Design,” IEEE Trans. on Computers, vol. C-39, pp. 538–544, April 1990.
T. Inoue, T. Hosokawa, T. Motohara, and H. Fujiwara, “An Optimal Time Expansion Model Based on CombinationalATPG for RT Level Circuits,” in Proc. Asian Test Symposium, 1998, pp. 190–197.
J. Jacob and V.D. Agrawal, “Multiple Fault Detection in Two-Level Multi-Output Circuits,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 171–173, 1992.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Inoue, M., Gizdarski, E. & Fujiwara, H. Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. Journal of Electronic Testing 18, 55–62 (2002). https://doi.org/10.1023/A:1013728006805
Issue Date:
DOI: https://doi.org/10.1023/A:1013728006805