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Hardware Design of FPGA-Based Embedded Heuristic Optimization Technique for Solving a Robotic Problem: IC-PSO

  • Research Article-Computer Engineering and Computer Science
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Abstract

In this study, a hardware design that runs the PSO algorithm at the micro level is carried out using FPGA technology, which facilitates prototyping and testing of integrated circuit systems. In this way, a high rate of acceleration has been achieved for swarm algorithms that perform stochastic search and whose calculation time is not suitable for real-time systems. For this, the inverse kinematics problem, which is used in the robotics field and which forms the basis of the robot control system, is solved for a 7-joint serial robot manipulator. Since the study aims to compare software-based calculations and hardware-based calculations, the results are presented in a comparative way with the results obtained with Matlab software. The tests have been performed in the study revealed two important situations. Firstly, the biggest handicap of algorithms such as PSO that reach a result by searching in a certain solution space is that the solution times are not suitable for real-time applications. The other is that FPGA can be used as a prototyping device for real-time applications due to its speed and hardware-based running. Because according to the test results, FPGA has accelerated the calculations up to 1000 times.

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Authors and Affiliations

  1. Computer Technology Department, Sakarya University of Applied Sciences, Sakarya, Turkey

    Serkan Dereli

  2. Electrical-Electronics Engineering, Sakarya University of Applied Sciences, Sakarya, Turkey

    Raşit Köker

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  1. Serkan Dereli
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  2. Raşit Köker
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Correspondence to Serkan Dereli.

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Dereli, S., Köker, R. Hardware Design of FPGA-Based Embedded Heuristic Optimization Technique for Solving a Robotic Problem: IC-PSO. Arab J Sci Eng 48, 10441–10455 (2023). https://doi.org/10.1007/s13369-023-07655-6

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