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Micro-sized parallel system design proposal for the solution of robotics based engineering problem

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Abstract

In this study, a hardware design that is micro-sized and capable of parallel processing is proposed for the solution of the most basic engineering problem required to control a serial robot manipulator. The proposed hardware design is in the form of FPGA-based digital circuit and has been realized in two different ways, serial and parallel. Forward kinematics problem solution of a 7-joint serial robot manipulator was used for the testing of the designed hardware. In order to the test results to be more objective, the same components were used for multiplication, division and trigonometric calculations in both series and parallel designs. IP-Core is used for multiplication and division operations, and Cordic algorithm is used for trigonometric calculations. The analysis of the results was carried out comparatively in terms of circuit size and solution time. As a result of the experiments, it has been clearly seen that though parallel architecture is more costly than serial architecture, it creates a difference of up to ten times in terms of time.

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References

  • Almadani B, Rashed A (2015) Enforce a reliable environment in parallel computing applications. Proc Comput Sci 63:24–31

    Article  Google Scholar 

  • Alonso RM, Lucio DT (2009) Parallel architecture for the solution of linear equation systems implemented in FPGA. In: Electronics, robotics and automotive mechanics conference, IEEE, pp 275–280.

  • Bahoura M, Ezzaidi H (2011) FPGA-implementation of parallel and sequential architectures for adaptive noise cancelation. Circuits Syst Signal Process 30:1521–1548

    Article  Google Scholar 

  • Chen W et al. (2016) FPGA-based parallel implementation of SURF algorithm. In: IEEE 22nd international conference on parallel and distributed systems (ICPADS), pp 308–315.

  • Dereli S, Köker R (2018) IW-PSO approach to the inverse kinematics problem solution of a 7-DOF serial robot manipulator. Int J Nat Eng Sci 36:75–85

    Google Scholar 

  • Dereli S, Köker R (2020) A meta-heuristic proposal for inverse kinematics solution of 7-DOF serial robotic manipulator: quantum behaved particle swarm algorithm. ArtifIntell Rev 53:949–964

    Google Scholar 

  • Du H, Qi H (2006) A reconfigurable FPGA system for parallel independent component analysis. EURASIP J Embed Syst 2006:1–12

    Article  Google Scholar 

  • Gomez-Pulido JA et al (2011) Accelerating floating-point fitness functions in evolutionary algorithms: a FPGA-CPU-GPU performance comparison. Genet Program Evol Mach 12:403–427

    Article  Google Scholar 

  • Gupta DK et al (2018) Real-time implementation of parallel architecture based noise minimization from speech signals on FPGA. WirelPersCommun 103:1941–1963

    Google Scholar 

  • Hailong S, Weipeng J, Boqi H (2019) Parallel computing of KNN query in road network based on MapReduce. Proc Comput Sci 147:381–388

    Article  Google Scholar 

  • Hayat AA et al. (2013) Identification of Denavit-Hartenberg parameters of an industrial robot. In: Proceedings of conference on advances in robotics, ACM, Pune, India, pp 1–6.

  • Huang H (2014) FPGA-based parallel metaheuristicPSO algorithm and its application to global path planning for autonomous robot navigation. J Intell Robot Syst 76:475–488

    Article  Google Scholar 

  • Huang B, Zhang H (2013) Application of multi-core parallel computing in FPGA placement. In: International symposium on instrumentation and measurement, sensor network and automation, IEEE, pp 884–889.

  • Iakymchuk R et al (2018) A taxonomy of task-based parallel programming technologies for high-performance computing. J Supercomput 74:1422–1434

    Article  Google Scholar 

  • Ibraheem MS et al (2017) High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform. J Real Time Image Process 16:2043–2057

    Article  Google Scholar 

  • Inam O et al (2020) FPGA-based hardware accelerator for SENSE (a parallel MR image reconstruction method). Comput Biol Med 117:103598

    Article  Google Scholar 

  • Joos A et al (2012) Method for parallel FPGA implementation of nonlinear model predictive control. IFACProc Vol 45:73–78

    Google Scholar 

  • Kogge P, Shalf J (2013) Exascale computing trends: adjusting to the “New Normal” for computer architecture. Comput Sci Eng 15:16–26

    Article  Google Scholar 

  • Kuhail MA et al. (2018) Teaching parallel programming with active learning. In: IEEE International parallel and distributed processing symposium workshops (IPDPSW), IEEE. Vancouver, BC, Canada

  • Li BMH, Leong PHW (2008) Serial and parallel FPGA-based variable block size motion estimation processors. J Signal Process Syst 51:77–98

    Article  Google Scholar 

  • Liu H et al (2013) An efficient inverse kinematic algorithm for a PUMA560-structured robot manipulator. Int J Adv Robot Syst 10:236–243

    Article  Google Scholar 

  • Lu Z et al (2019) Parallel computing method of deep belief networks and its application to traffic flow prediction. Knowl Based Syst 163:972–987

    Article  Google Scholar 

  • Martineau M et al. (2016) An evaluation of emerging many-core parallel programming models. In: Proceedings of the 7th international workshop on programming models and applications for multicores and manycores, Barcelona, Spain, pp 1–10.

  • Mukherjee D, Mukhopadhyay S, Biswas GP (2017) FPGA-based parallel implementation of morphological operators for 2D gray-level images. Arab J Sci Eng 42:3191–3206

    Article  Google Scholar 

  • Noronha DH, Torquato MF, Fernandes MA (2019) A parallel implementation of sequential minimal optimization on FPGA. MicroprocessMicrosyst 69:138–151

    Google Scholar 

  • Parhi DR et al (2012) Forward and inverse kinematic models for an articulated robotic manipulator. Int J ArtifIntell Comput Res 4:103–109

    Google Scholar 

  • Roy SS et al. (2019) FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data. In: IEEE international symposium on high performance computer architecture (HPCA), pp 387–398.

  • Şahin S, Savaş BK (2017) Hardware iplementation of generic CORDIC algorithm on FPGA. Sakarya Univ J Sci 21:16–25

    Article  Google Scholar 

  • Shafiq M et al (2020) Accelerating fingerprint identification using FPGA for large-scale applications. J Parallel Distrib Comput 141:35–48

    Article  Google Scholar 

  • Singh S, Greaves DJ (2008) Kiwi: synthesis of FPGA circuits from parallel programs. In: International symposium on field-programmable custom computing machines, IEEE, pp 3–12.

  • Sosutha S, Mohana D (2015) Heterogeneous parallel computing using cuda for chemical process. Proc Comput Sci 47:237–246

    Article  Google Scholar 

  • Stojilović M (2017) Parallel FPGA routing: survey and challenges. In: International conference on field programmable logic and applications (FPL), IEEE, Ghent, Belgium

  • Sulaiman N, Obaid ZA, Marhaban MH, Hamidon MN (2009) Design and implementation of FPGA-based systems—a review. Aust J Basic Appl Sci 3:3575–3596

    Google Scholar 

  • Tan XY, Boland D, Constantinides G (2012) FPGA paranoia: testing numerical properties of FPGA floating point IP-cores. In: International symposium on applied reconfigurable computing, Berlin: Springer, pp 290–301.

  • Tripathi A et al. (2017) A transactional model for parallel programming of graph applications on computing clusters. In: International conference on cloud computing (CLOUD), IEEE, Honolulu, CA, USA

  • Unlersen FM, Yaldiz E, Imeci ST (2018) FPGA based fast Bartlett DoA estimator for ULA antenna using parallel computing. Appl Comput ElectromagnSoc J 33:450–459

    Google Scholar 

  • Vostokin SV (2017) The templet parallel computing system: specification, implementation, applications. ProcEng 201:684–689

    Google Scholar 

  • Zeebaree SR et al. (2019) Design and simulation of high-speed parallel/sequential simplified DES code breaking based on FPGA. In: International conference on advanced science and engineering (ICOASE), pp 76–81.

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  1. Sakarya University of Applied Sciences, Computer Technology and Programming, Serdivan, Sakarya, Turkey

    Serkan Dereli

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  1. Serkan Dereli
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Correspondence to Serkan Dereli.

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Dereli, S. Micro-sized parallel system design proposal for the solution of robotics based engineering problem. Microsyst Technol 27, 4217–4226 (2021). https://doi.org/10.1007/s00542-020-05209-6

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