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A Transient-Enhanced Low-Power Standard-Cell-Based Digital LDO

  • Research Article-Electrical Engineering
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Abstract

In this article, a transient-enhanced fully synthesizable digital low dropout regulator (FS-DLDO) is proposed for ultra-low-power applications. The FS-DLDO uses a fully synthesizable comparator (FS-Com) to sense load variations. A digital logic controller (D-CTRL) tunes the output voltage (VO) through a quad-loop architecture. The quad-loop architecture uses short bidirectional shift registers (BSR) to achieve fast-transient response and reduce leakage current. In addition, the FS-DLDO supports freeze-mode to regulate a ripple-free VO and minimize power consumption at a steady state. To demonstrate this entire design using standard-cells, the P-MOSFET array (PTA) used in traditional digital low dropout regulator (DLDO) is replaced with an array of three-state buffers (TSA). The layout is created using digital design flow in TSMC CMOS 45 nm process, which occupies a 6708 µm2 area. For a power supply (VSUP) range of 0.5–1 V, the FS-DLDO can provide regulated VO with a 50 mV dropout voltage. At VSUP = 500 mV and clock frequency (fCLK) of 10 MHz, the proposed regulator achieves a transient response time of 0.91 µs. This prototype achieves a peak current efficiency of 99.90% and produces a ripple-free VO at a steady state.

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Abbreviations

A-LDO:

Analog low dropout regulator

BSR:

Bidirectional shift register

CMV:

Common-mode voltage

CT:

Coarse-tuning

D-LDO:

Digital low dropout regulator

D-CTRL:

Digital logic controller

f CLK :

Clock frequency

FOM:

Figure of merit

FS-Com:

Fully synthesizable comparator

FS-DLDO:

Fully synthesizable D-LDO

FT:

Fine-tuning

I MAX :

Maximum load current

I OUT :

Load current

I Q :

Quiescent current

MT:

Medium-tuning

NAND-Com:

NAND-based comparator

NOR-Com:

NOR-based comparator

OUD:

Overshoot/undershoot detector

PTA:

P-MOSFET array

PnR:

Place-and-Route

QT:

Quivering

QTU:

Quivering control unit

TCU:

Tuning control unit

TSA:

Three-state buffer array

V O :

Output voltage

V R :

Reference voltage

V RES :

Voltage step resolution

V SUP :

Supply voltage

VtINV :

Switching threshold of INV cell

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Acknowledgements

The authors would like to thank Thapar Institute of Engineering & Technology (TIET) for providing the laboratory facilities to conduct the proposed research. The authors also wish to thank Ministry of Electronics & Information Technology (MEITY), Government of India, for funding the research through SMDP-C2SD project.

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Authors and Affiliations

  1. Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology (TIET), Patiala, India

    Lalit Sood & Alpana Agarwal

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  1. Lalit Sood
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Correspondence to Alpana Agarwal.

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Sood, L., Agarwal, A. A Transient-Enhanced Low-Power Standard-Cell-Based Digital LDO. Arab J Sci Eng 47, 13943–13953 (2022). https://doi.org/10.1007/s13369-022-06592-0

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