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Drain Source-Engineered Double-Gate Tunnel FET for Improved Performance

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Abstract

The present study proposes an approach to enhance the DC and RF performance parameters of a double-gate tunnel field-effect transistor (DGTFET). The approach integrates an extended source with stacked drain layers of varying doping concentrations. This integration results in a drain-engineered extended source double-gate tunnel FET (DE-ES-DGTFET), demonstrating low ambipolarity and abrupt switching. The source and drain engineering enable the device to increase the ON-current while simultaneously reducing ambipolarity due to the large tunneling area with different drain doping concentrations. The optimization of the device's performance parameters was carried out by varying the doping concentration of the stacked drain, source length, and thickness of the drain. The proposed device achieved significant improvements compared to conventional DGTFETs, including a two-decade reduction in ambipolar current, an order of improvement in the ON-current (ION) of ~ 10−5 A/µm, two orders of reduction in ambipolarity (IAmb) 5.91 × 10−17 A/µm, two orders of enhancement in ratio ION/IOFF of − 1013, a subthreshold swing (SS) of 23.3 mV/dec, and nearly a two-fold increase in cut-off frequency (fT), and a transit time (\(\tau\)) ~ 80 ps have been accomplished.

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Authors and Affiliations

  1. School of VLSI Design and Embedded Systems, NIT Kurukshetra, Kurukshetra, Haryana, India

    Arashpreet Kaur & Gaurav Saini

  2. Department of Electronics and Communication Engineering, NIT Kurukshetra, Kurukshetra, Haryana, India

    Gaurav Saini

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  1. Arashpreet Kaur
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Kaur, A., Saini, G. Drain Source-Engineered Double-Gate Tunnel FET for Improved Performance. J. Electron. Mater. (2024). https://doi.org/10.1007/s11664-024-11109-6

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