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RF dual-gate-trench LDMOS on InGaAs with improved performance

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Abstract

A new power dual-gate-trench LDMOSFET (DGTLDMOS) structure implemented on emerging InGaAs material is proposed. The proposed device consists of two gates out of which one gate is placed horizontally on the surface while other gate is located vertically in a trench. The dual-gate structure of DGTLDMOS creates two channels in p-base which carry current simultaneously from drain to source. This not only enhances the drain current (ID) but also reduces specific on-resistance (Ron,sp) and improves the peak transconductance (gm) resulting higher cut-off frequency (fT) and maximum oscillation frequency (fmax). Another trench filled with Al2O3 is placed in the drift region between gate and drain to enhance reduced-surface-field effect leading to higher breakdown voltage (Vbr) even at increased drift region doping. Based on 2D simulations, it is demonstrate that a DGTLDMOS designed for Vbr of 90 V achieves 2.2 times higher ID, 10 times reduction in Ron,sp, 1.8 times improvement in gm, 2.8 times increase in fT, and 1.8 times improvement in fmax with 3.3 times reduction in cell pitch as compared to the conventional LDMOS.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand, 246 194, India

    M. Payal & Y. Singh

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  1. M. Payal
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  2. Y. Singh
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Correspondence to M. Payal.

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Payal, M., Singh, Y. RF dual-gate-trench LDMOS on InGaAs with improved performance. Indian J Phys 92, 151–157 (2018). https://doi.org/10.1007/s12648-017-1086-z

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  • DOI: https://doi.org/10.1007/s12648-017-1086-z

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