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Recent Advances in Gate Dielectrics for Enhanced Leakage Current Management and Device Performance

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Abstract

Gate oxide in metal oxide semiconductor field effect transistor (MOSFET) or gate dielectric layer in thin film transistor (TFT) plays an important role in the inhibition of leakage current. Thus, high-quality of insulating properties (> 10 MV/cm) and high resistance of gate dielectric have been required. The dimension of gate oxide needs to be reduced for the amplified on-current and switching speed. However, the dimension of the oxide, developed so far, has reached its limit, and leakage current is inevitable. The structural, processing, and material methods were categorically discussed to improve insulating properties in TFT and MOSFET for leakage reduction. The parameters including threshold voltage, subthreshold swing (SS), and off current of developed devices were compared in this paper. Through advanced structure application such as GAA, capacitorless DRAM, and hybrid dielectrics, MOSFETs could be scaled down with minimum leakage current. This review paper has been divided into sections covering structural, material, and process developments that have been researched to date. After briefly explaining each of these aspects, the paper concludes by proposing the application of NO precursor as a novel reactant material, deuterium-passivation, and process parameter optimization to address the current reduction for further research.

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Abbreviations

TFT:

Thin-film transistor

FET:

Field-effect transistor

LCD:

Liquid crystal display

IGZO:

Indium-gallium-zinc-oxide

MOS:

Metal-oxide-semiconductor

SCE:

Short channel effect

SOI:

Silicon on oxide

DIBL:

Drain-induced barrier lowering

DB:

Double gate

JL:

Junction-less

GAA:

Gate-all-around

LTPS:

Low-temperature polysilicon

MBC:

Multi bridge channel

LDD:

Lightly doped drain

SS:

Subthreshold swing

OFET:

Organic field effect transistor

DDBPA:

1,12-Dodecanediylbis (phosphonic acid)

ODPA:

N-Octadecyl phosphonic acid

DHDP:

4,4′-Dihydroxydipheny1

EPOXY:

Epoxy resin

TGA:

Thermo-gravimetric analysis

OSC:

Organic solar cell

PEN:

Polyethylene naphthalene

DELTA:

Depleted lean channel transistor

References

  1. R.R. Schaller, Moore’s law: past, present and future. IEEE Spectr. 34(6), 52–59 (1997)

    Article  Google Scholar 

  2. D.P. Pham et al., In-situ PECVD-based stoichiometric SiO2 layer for semiconductor devices. Opt. Mater. (Amst) 137, 113536 (2023)

    Article  CAS  Google Scholar 

  3. A. Veloso et al., Gate-all-around NWFETs versus triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS, in 2015 Symposium on VLSI Technology (VLSI Technology) (IEEE, 2015), pp. T138–T139

  4. J.S. Jur, Lanthanide-based oxides and silicates for high-k gate dielectric applications (2007)

  5. Y.-K. Choi et al., Ultrathin-body SOI MOSFET for deep-sub-tenth micron era. IEEE Electron Device Lett. 21(5), 254–255 (2000). https://doi.org/10.1109/55.841313

    Article  CAS  Google Scholar 

  6. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, Scaling theory for double-gate SOI MOSFET’s. IEEE Trans. Electron Devices 40(12), 2326–2329 (1993)

    Article  CAS  Google Scholar 

  7. D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda, A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET, in International Technical Digest on Electron Devices Meeting (IEEE, 1989), pp. 833–836

  8. K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q, in Digest. International Electron Devices Meeting (IEEE, 2002), pp. 289–292

  9. S. Datta, H. Liu, V. Narayanan, Tunnel FET technology: a reliability perspective. Microelectron. Reliab. 54(5), 861–874 (2014)

    Article  Google Scholar 

  10. A.M. Ionescu, Nanowire transistors made easy. Nat. Nanotechnol. 5(3), 178–179 (2010)

    Article  CAS  PubMed  Google Scholar 

  11. E. Yoshida, T. Tanaka, A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory. IEEE Trans. Electron Devices 53(4), 692–697 (2006)

    Article  CAS  Google Scholar 

  12. D.K. Ngwashi, T.A. Mih, The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors. Sci. Afr. 20, e01653 (2023)

    CAS  Google Scholar 

  13. Q. Huang et al., Intrinsically flexible all-carbon-nanotube electronics enabled by a hybrid organic–inorganic gate dielectric. npj Flex. Electron. 6(1), 61 (2022)

    Article  CAS  Google Scholar 

  14. F. Schwierz, Graphene transistors. Nat. Nanotechnol. 5(7), 487–496 (2010)

    Article  CAS  PubMed  Google Scholar 

  15. H.L.M. Toan, S.S. Singh, S.K. Maity, Analysis of temperature effect in quadruple gate nano-scale finfet. SILICON 13, 2077–2087 (2021)

    Article  CAS  Google Scholar 

  16. X. Lin, B. Zhang, Y. Xiao, H. Lou, L. Zhang, M. Chan, Analytical current model for long-channel junctionless double-gate MOSFETs. IEEE Trans. Electron Devices 63(3), 959–965 (2016)

    CAS  Google Scholar 

  17. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, J.G. Fossum, TCAD-based assessment of the lateral GAA nanosheet transistor for future CMOS. IEEE Trans. Electron Devices 68(12), 6586–6591 (2021)

    Article  CAS  Google Scholar 

  18. A.O. Adan, D. Tanaka, L. Burgyan, Y. Kakizaki, The current status and trends of 1200-V commercial silicon-carbide MOSFETs: deep physical analysis of power transistors from a designer’s perspective. IEEE Power Electron. Mag. 6(2), 36–47 (2019)

    Article  Google Scholar 

  19. A. Lazzaz, K. Bousbahi, M. Ghamnia, Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM, 7 NM and 5 NM node technologies. Facta Univ. Electron. Energy 36(1), 1–16 (2023)

    Article  Google Scholar 

  20. P. Kumar, M. Vashishath, N. Gupta, R. Gupta, High-k dielectric double gate junctionless (DG-JL) MOSFET for ultra low power applications-analytical model. SILICON 8, 1–10 (2022)

    Google Scholar 

  21. K. Choe, C. Shin, Adjusting the operating voltage of an nanoelectromechanical relay using negative capacitance. IEEE Trans. Electron Devices 64(12), 5270–5273 (2017)

    Article  CAS  Google Scholar 

  22. E.S. Yu et al., Low voltage a-IGZO thin film transistor using tantalum oxide by thermal oxidation. Electron. Mater. Lett. 6, 1–9 (2023)

    Google Scholar 

  23. Y.-W. Kim, Y.-G. Ha, Organic-inorganic hybrid gate dielectrics using self-assembled multilayers for low-voltage operating thin-film transistors. Korean J. Met. Mater. 60(3), 220–226 (2022)

    Article  CAS  Google Scholar 

  24. K. Kuribara et al., Organic transistors with high thermal stability for medical applications. Nat. Commun. 3(1), 723 (2012)

    Article  PubMed  Google Scholar 

  25. T. Xu et al., Newly synthesized high-k polymeric dielectrics with cyclic carbonate functionality for highly stability organic field-effect transistor applications. Adv. Electron. Mater. 9(1), 2200984 (2023)

    Article  CAS  Google Scholar 

  26. E.L. Yuan, J.I. Slaughter, W.B. Koerner, F. Daniels, Kinetics of the decomposition of nitric oxide in the range 700–1800°. J. Phys. Chem. 63(6), 952–956 (1959)

    Article  CAS  Google Scholar 

  27. Y.J. Tak et al., Reduction of activation temperature at 150 °C for IGZO films with improved electrical performance via UV-thermal treatment. J. Inf. Disp. 17(2), 73–78 (2016)

    Article  CAS  Google Scholar 

  28. Y. Yu, N. Lv, D. Zhang, Y. Wei, M. Wang, High-mobility amorphous InGaZnO thin-film transistors with nitrogen introduced via low-temperature annealing. IEEE Electron Device Lett. 42(10), 1480–1483 (2021)

    Article  CAS  Google Scholar 

  29. O.K. Prasad, S.K. Mohanty, C.H. Wu, T.Y. Yu, K.M. Chang, Role of in-situ hydrogen plasma treatment on gate bias stability and performance of a-IGZO thin-film transistors. Nanotechnology 32(39), 395203 (2021)

    Article  CAS  Google Scholar 

  30. W.-S. Liu, C.-H. Hsu, Y. Jiang, Y.-C. Lai, H.-C. Kuo, Improving device characteristics of dual-gate IGZO thin-film transistors with Ar–O2 mixed plasma treatment and rapid thermal annealing. Membranes (Basel) 12(1), 49 (2021)

    Article  PubMed  Google Scholar 

  31. M.K. Lee et al., Electro-thermal annealing method for recovery of cyclic bending stress in flexible a-IGZO TFTs. IEEE Trans. Electron Devices 64(8), 3189–3192 (2017)

    Article  CAS  Google Scholar 

  32. T.T. Trinh et al., Improvement in the performance of an InGaZnO thin-film transistor by controlling interface trap densities between the insulator and active layer. Semicond. Sci. Technol. 26(8), 85012 (2011)

    Article  Google Scholar 

  33. J.-Y. Lee, K.-J. Heo, S.-G. Choi, H.G. Ryu, J.-H. Koh, S.-J. Kim, Effects of oxygen injection rates on a-IGZO thin-film transistors with oxygen plasma treatment. J. Semicond. Technol. Sci 21, 189–198 (2021)

    Article  CAS  Google Scholar 

  34. S.-I. Oh, G. Choi, H. Hwang, W. Lu, J.-H. Jang, Hydrogenated IGZO thin-film transistors using high-pressure hydrogen annealing. IEEE Trans. Electron Devices 60(8), 2537–2541 (2013)

    Article  CAS  Google Scholar 

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Funding

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2022R1A4A1028702). This work was also supported by the Technology Innovation Program (or Industrial Strategic Technology Development Program) (RS-2023-00266568) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

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Correspondence to Duy Phong Pham or Junsin Yi.

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Jeong, Y., Cho, J., Pham, D.P. et al. Recent Advances in Gate Dielectrics for Enhanced Leakage Current Management and Device Performance. Trans. Electr. Electron. Mater. (2024). https://doi.org/10.1007/s42341-024-00531-6

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  • DOI: https://doi.org/10.1007/s42341-024-00531-6

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