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Performance Assessments of Gate Engineered Dopingless Schottky Tunnel MOSFET in Presence of Interfacial Trap Charges

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Abstract

The most notable accumulation of trap charges occurs on the oxide/semiconductor interface of MOS devices and it degrades the device’s performance and reliability. In this literature, we proposed a gate-engineered Schottky tunneling MOSFET(GE-ST-MOSFET) for ON state performance improvement, and a detailed analysis of the effects of interface trap charges (ITCs) on the DC characteristics and analog/RF performance metrics have been analyzed. In this device, the electrostatically doping-based dopant segregation layer (DSL) is introduced at the source side in the channel end by the Tunneling Gate(TG). A comparative study between the proposed GE-ST-MOSFET and conventional Schottky tunneling MOSFET(ST-MOSFET) has been carried out in presence of interface trap charges at the \(\textrm{HfO}_{2}\)/Si interface. A significant improvement in \(\textrm{I}_{\textrm{ON}}\) and \(\textrm{I}_{\textrm{ON}}/\textrm{I}_{\textrm{OFF}}\) ratio has been achieved 563 \(\times \) and 1472\(\times \) respectively in the GE-ST-MOSFET as compared to the ST-MOSFET. To analyze the linearity behavior, higher-order transconductance parameters are also studied considering the effect of ITCs. Furthermore, the circuit-level performances of both devices are analyzed using the Verilog-A based models. The effect of OFF current variation on switching performance has been investigated. It has been found that the average switching delay and Power Delay Product (PDP) have improved by 97% and 81% respectively in comparison to the conventional device-based inverter. The GE-ST-MOSFET-based circuit also shows better immunity to interface trap charges. In addition, the implementation of the electrostatically doping concept for the proposed device could make fabrication very simple.

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Acknowledgements

The authors acknowledge Dr. Kunal Singh, Assistant Professor of NIT Jamshedpur for providing the Silvaco TCAD tool. The authors also acknowledge the SMDP-C2SD Project under the Government of India for providing the Cadence Virtuoso Tool.

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  1. ECE, NIT Sikkim, Ravangla, 737139, Sikkim, India

    Arnab Som & Sanjay Kumar Jana

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  1. Arnab Som
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Author 1 (Arnab Som) Prepared the outline, conducted the simulation and analyzed the whole work, and prepared the manuscript. Author 2 (Sanjay Kumar Jana) Supervised the whole work and thoroughly revised the manuscript. The author(s) read and approved the final manuscript.

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Correspondence to Arnab Som.

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Som, A., Jana, S.K. Performance Assessments of Gate Engineered Dopingless Schottky Tunnel MOSFET in Presence of Interfacial Trap Charges. Silicon 15, 7265–7278 (2023). https://doi.org/10.1007/s12633-023-02504-5

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