Abstract
One of the most promising device configurations for extending CMOS device scaling is the gate-all-around MOSFET since it provides excellent electrostatic control of the channel. In this work, hetero-dielectric single-metal gate-all-around MOSFETs with Schottky contact source/drain are designed and analyzed using COGENDA Visual TCAD. Through device simulations in a TCAD framework, the electrical properties of the devices, such as ON-current, leakage current, and subthreshold swing, have been examined. The proposed device features an unsymmetrical oxide geometry with Schottky source/drain regions and high-k (HfxTi1−xO2) on the source side (length dimension = 15 nm) and SiO2 on the drain side (length dimension = 5 nm), respectively. The design of the suggested device has taken into account physical theories including drift–diffusion, Lombardi mobility, band-to-band tunneling, and the Shockley–Read–Hall carrier recombination process. The proposed device offers reduced OFF-current and suppressed SCEs. Compared to conventional GAA MOSFET, leakage currents are dropped to a level between 10−15 and 10−9 A. With a subthreshold swing of 62.7 mV dec−1, which almost achieves the ideal value, the device exhibits impressive subthreshold region performance. It has exceptionally low static power consumption due to decreased leakages, which makes it ideal for low-voltage and low-power digital execution. According to device modeling analysis, the hetero-dielectric single-metal gate-all-around MOSFET with Schottky contact source/drain is a strong design for convenience in low-power digital circuitry.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Shailaja J, Priya YY (2017) A brief study on challenges of MOSFET and evolution of FINFETs. In: International conference on emerging trends in engineering, science and management, vol 05, no 03
Gautam R, Saxena M, Gupta RS, Gupta M (2013) Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance. IEEE Trans Electron Devices 60:1820–1827
Wikipedia, https://en.wikipedia.org/wiki/Nanowire, last accessed 2023/03/15
Signoffsemiconductors, https://signoffsemiconductors.com/gate-all-around-fet/, last accessed 2023/02/22
Kaur A, Mehra R, Saini A (2019) Hetero-dielectric oxide engineering on dopingless gate all around nanowire MOSFET with Schottky contact source/drain. AEU Int J Electron Commun 152888
Connelly D, Faulkner C, Clifton PA, Grupp DE (2006) Fermi-level depinning for low-barrier Schottky source/drain transistors. Appl Phys Lett 88:012105
Kumar A, Pattanaik M, Srivastava P, Jha KK (2020) Reduction of drain induced barrier lowering in DM-HD-NA GAAFET for RF applications. IET Circ Dev Syst 14:270–275
Barraud S, Lapras V, Previtali B, Samson MP, Lacord J, Martinie S, Jaud M-A, Athanasiou S, Triozon F, Rozeau O, Hartmann JM, Vizioz C, Comboroure C, Andrieu F, Barbe JC, Vinet M, Ernst T (2017) Performance and design considerations for gate-all-around stacked-nanowires FETs. In: 2017 IEEE international electron. devices meeting (IEDM)
Sinha SK, Kumar K, Chaudhury S (2015) Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices. In: 2015 IEEE international conference on electron devices and solid-state circuits (EDSSC), pp 527–530
Robertson J (2004) High dielectric constant oxides. Eur Phys J Appl Phys 28:265–291
Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2017) Gate-induced drain leakage reduction in cylindrical dual-metal hetero-dielectric gate all around MOSFET. IEEE Trans Electron Dev 1–8
Kaur G, Gill SS, Rattan M (2020) Impact of lanthanum doped zirconium oxide (LaZrO2) gate dielectric material on FinFET inverter. Int J Smart Sens Intell Syst 13:1–10
Kaur N, Rattan M, Gill SS (2019) Design and optimization of novel shaped FinFET. Arab J Sci Eng 44:3101–3116
Genius semiconductor device simulator reference manual
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Devi, R., Kaur, G. (2023). Design of Hetero-Dielectric Single-Metal Gate-All-Around MOSFET with Schottky Contact Source/Drain. In: Khan, Z.H., Jackson, M., Salah, N.A. (eds) Recent Advances in Nanotechnology. ICNOC 2022. Springer Proceedings in Materials, vol 28. Springer, Singapore. https://doi.org/10.1007/978-981-99-4685-3_1
Download citation
DOI: https://doi.org/10.1007/978-981-99-4685-3_1
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-99-4684-6
Online ISBN: 978-981-99-4685-3
eBook Packages: Chemistry and Materials ScienceChemistry and Material Science (R0)