Abstract
This work presents the design and simulation of a novel double-gate L-shaped Schottky barrier MOSFET (DG-LS-SB-MOSFET). The device uses a low work function metal near source-channel junction and ErSi1.4 at source and drain regions. Simulated results show that DG-LS-SB-MOSFET has successfully improved the SCE parameters and exhibits high on-current (241 µA/µm) and 2.2 × 103 times higher ION/IOFF as that of conventional device (DG-SB-MOSFET). Due to the use of HfO2 as gate oxide, there is a change of 37.5% in sub-threshold swing (SS). DG-LS-SB-MOSFET also shows similar improvements in RF/analog parameters such as output conductance (gd), transconductance generation factor (gm/ID), Early voltage (VEA), intrinsic gain, cut-off frequency (fT), Gain Frequency Product (GFP) and Gain Transconductance Frequency Product (GTFP). Using 2D calibrated simulation, we validated the transfer characteristics of SB-FET. Furthermore, DG-LS-SB-MOSFET based inverter shows a reduction in ON delay of 95.31% and 46.72% in OFF delay in the as compared to the conventional device-based inverter.
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References
Skotnicki T, Hutchby JA, King TJ, Wong H-SP, Boeuf F (2005) The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Devices Mag 21(1):16–26
Shah KA, Khanday FA (2020) Nanoscale Electronic Devices and Their Applications. CRC Press, Boca Raton
Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review. IEEE Trans Device Mater Rel 4(1):99–109
Wang C, Snyder JP, Tucker JR (1998) Sub-50-nm PtSi Schottky source/drain p-MOSFETs. In: Proc. 56th Annu. Device Res. Conf. Dig., pp. 72–73
Itoh A, Saitoh M, Asada M (2000) Very short channel metal-gate Schottky source/drain SOI-PMOSFETs and their short channel effect. In: Proc. 58th Annu. Device Res. Conf. Dig., pp. 77–78
Ostling M, Luo J, Gudmundsson V, Hellström PE, Malm BG (2010) Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts. Proc. 27th Int. Conf. Microelectron, pp 9–13
Larrieu G, Yarekha DA, Dubois E, Breil N, Faynot O (2009) Arsenic-segregated rare-earth silicide junctions: Reduction of Schottky barrier and integration in metallic n-MOSFETs on SOI. IEEE Electron Device Lett 30(12):1266–1268
Vega R, Liu TJK (2010) Dopant-segregated Schottky junction tuning with fluorine pre-silicidation ion implant. IEEE Trans Electron Devices 57(5):1084–1092
Snyder JP (1996) The physics and technology of platinum silicide source and drain field effect transistors. Ph.D. dissertation, Dept. Elect. Electron., Stanford Univ., Stanford, CA, USA
Larrieu G, Dubois E (2004) Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate. IEEE Electron Device Lett 25(12):801–803
Patil GC, Qureshi S (2011) A novel δ-doped partially insulated dopant segregated Schottky barrier SOI MOSFET for analog/RF applications. Semicond Sci Technol 26(8):085002
Larrieu G, Dubois E (2011) CMOS inverter based on Schottky source–drain MOS technology with low-temperature dopant segregation. IEEE Electron Device Lett 32(6):728–730
Bashir F, Loan SA, Rafat M, Alamoud ARM, Abbasi SA (2015) A high-performance source engineered charge plasma-based Schottky MOSFET on SOI. IEEE Trans Electron Devices 62(10):3357–3364
Bashir F, Alharbi AG, Loan SA (2017) Electrostatically Doped DSL Schottky Barrier MOSFET on SOI for Low Power Applications. IEEE J Electron Devices Soc 6:19–25
Hirpara Y, Saha R (2020) Analysis on DC and RF/analog performance in multifin-FinFET for wide variation in work function of metal gate. SILICON 13(1):73–77
Kaushal S, Rana AK (2021) Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach. Silicon, pp.1–10
Kaushal S, Rana AK (2022) Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET. Microelectron J 121:105382
Kaushal S, Rana AK (2021) Analytical modelling and simulation of negative capacitance junctionless FinFET considering fringing field effects”. Superlattices Microstruct 155:106929
Roy A, Mitra R, Mondal A, Kundu A (2021) Analog/RF and Power Performance Analysis of an Underlap DG AlGaN/GaN Based High-K Dielectric MOS-HEMT. SILICON 14:221–228
Kaushal S, Rana AK, Sharma R (2021) Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling. SILICON 13(10):3681–3690
Lepselter MP, Sze SM (1968) SB-IGFET: an insulated-gate field effect transistor using Schottky barrier contacts for source and drain. Proc IEEE 56(8):1400–1402
Calvet LE, Luebben H, Reed MA, Wang C, Synder JP, Tucker JR (2000) Subthreshold and scaling of PtSi Schottky barrier MOSFETs. Superlattices Microstruct 28(5–6):501–506
Tucker JR (1997) Schottky barrier MOSFETs for silicon nanoelectronics. In: Proc. IEEE Workshop Frontier Electron, pp. 97–100
Knoch J, Zhang M, Mantl S, Appenzeller J (2006) On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs. IEEE Trans Electron Devices 53(7):1669–1673
Zhang M, Knoch J, Appenzeller J, Mantl S (2007) Improved carrier injection in ultrathin-body SOI Schottky-barrier MOSFETs. IEEE Electron Device Lett 28(3):223–225
Zhu S, Yu HY, Chen JD, Whang SJ, Chen JH, Shen C, Zhu C, Lee SJ, Li MF, Chan DSH, Yoo WJ (2004) Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode. Solid-State Electron 48(10–11):1987–1992
Atlas (2017) TCAD device simulator, Silvaco TCAD software
Guilmain M, Jaouad A, Ecoffey S, Drouin D (2011) SiO2 shallow nanostructures ICP etching using ZEP electroresist. Microelectron Eng 88(8):2505–2508
Jang M, Kim Y, Shin J, Lee S (2004) A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor. Appl Phys Lett 84(5):741–743
Kedzierski J, Xuan P, Erik EK, Anderson H, Bokor J, King T-J, Hu C (2000) Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime. IEDM. Tech Dig 57–60
Zhang X-Y, Hsu C-H, Lien S-Y, Chen S-Y, Huang W, Yang C-H, Kung C-Y, Zhu W-Z, Xiong F-B, Meng X-G (2017) Surface passivation of silicon using HfO2 thin films deposited by remote plasma atomic layer deposition system. Nanosc Res Lett 12(1):1–7
Alfaraj N, Rasheedi NA Fabrication Simulation of a Flexible Metal─Oxide─Semiconductor Field-Effect Transistor. https://doi.org/10.13140/RG.2.2.32243.12324/1
Jhaveri R, Nagavarapu V, Woo JCS (2009) Asymmetric Schottky tunneling source SOI MOSFET design for mixed-mode applications. IEEE Trans Electron Devices 56(1):93–99
Fritze M, Chen CL, Calawa S, Yost D, Wheeler B, Wyatt P, Larson J (2004) High-speed Schottky-barrier pMOSFET with f/sub T/= 280 GHz. IEEE Electron Device Lett 25(4):220–222
Chin YK, Pey KL, Singh N, Lo GQ, Tan KH, Ong CY, Tan LH (2009) Dopant-segregated Schottky silicon-nanowire MOSFETs with gate-all-around channels. IEEE Electron Device Lett 30(8):843–845
Tan EJ, Pey KL, Singh N, Lo GQ, Chi DZ, Chin YK, Lee PS (2008) Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel. IEEE Electron Device Lett 29(10):1167–1170
Kumar P, Bhowmick B (2020) Source-Drain Junction Engineering Schottky Barrier MOSFETs and their Mixed Mode Application. SILICON 12(4):821–830
Kumar P, Bhowmick B (2018) Scaling of dopant segregation Schottky barrier using metal strip buried oxide MOSFET and its comparison with conventional device. SILICON 10(3):811–820
Rashid S, Bashir F, Khanday FA, Beigh MR, Hussin FA (2021) 2-D Design of Double Gate Schottky Tunnel MOSFET for High-Performance Use in Analog/RF Applications. IEEE Access 9:80158–80169
Acknowledgements
The research work is supported by University Grants Commission, Government of India in the form of Junior Research Fellowship (190510736394).
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Ms. Shazia Rashid-Conceptualization, Methodology, Software, Investigation, Writing -original draft preparation, Editing, Reviewing; Dr. Faisal Bashir-Data curation, Visualization, Investigation, Software, Editing, Revision; Dr. Farooq A. Khanday-Supervision, Reviewing, Revision and Editing; Dr. M. Rafiq Beigh- Reviewing and Editing.
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Rashid, S., Bashir, F., Khanday, F.A. et al. L-Shaped Schottky Barrier MOSFET for High Performance Analog and RF Applications. Silicon 15, 205–215 (2023). https://doi.org/10.1007/s12633-022-02006-w
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DOI: https://doi.org/10.1007/s12633-022-02006-w