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Effect of Process-Induced Variations on Analog Performance of Silicon based Nanosheet Transistor

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Abstract

The reliability of Silicon-based nanosheet transistors (NSTs) is limited by process-induced variations (PIVs) like work-function-variations (WFV), line-edge-roughness (LER), gate-edge-roughness (GER), sheet-thickness-variation (STV), etc. This study reports the overall effect of PIVs on the analog performance of 5-nm node n-channel NST, with gate length and width of 12 nm and 15 nm, respectively, using a fully calibrated TCAD platform. NST’s transconductance (gm) and output conductance (gds) are strongly affected by PIVs, leading to as much as ~ 23% change in intrinsic gain (Av) and gain-frequency-product (GFP) values. Variations in discharge-time (td) values of NST indicate that the average drive current can vary between ~ -17.4% and ~ 24.4% of the typical value. Also, the PIVs cause NST’s unit-gain-frequency (fT) to vary by ~ 1.4%.

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Authors and Affiliations

  1. National Institute of Technology Uttarakhand, Srinagar Garhwal, Uttarakhand, 246174, India

    Yogendra Pratap Pundir, Arvind Bisht, Rajesh Saha & Pankaj Kumar Pal

  2. Hemvati Nandan Bahuguna Garhwal University, Srinagar Garhwal, Uttarakhand, 246174, India

    Yogendra Pratap Pundir

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  1. Yogendra Pratap Pundir
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  2. Arvind Bisht
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Contributions

Yogendra Pratap Pundir has contributed to the Conceptualization, Methodology, Writing of Original Draft, Software, Data Curation, Investigation, and Editing. Arvind Bisht and Rajesh Saha have contributed to the Formal analysis. Pankaj Kumar Pal has contributed to the Formal analysis and Editing of this paper. All authors have contributed to the review and revision of this paper.

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Correspondence to Yogendra Pratap Pundir.

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Pundir, Y.P., Bisht, A., Saha, R. et al. Effect of Process-Induced Variations on Analog Performance of Silicon based Nanosheet Transistor. Silicon 15, 4449–4455 (2023). https://doi.org/10.1007/s12633-023-02365-y

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