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Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

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Abstract

Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical configurations of the NSFET. In this script, the DC performance of 3D GAA NSFET is analyzed by varying the device's width and thickness. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability for continuous scaling in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm and 10 to 50 nm, respectively, to analyze the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (ION), off current (IOFF), switching ratio (ION/IOFF), threshold voltage (Vth), and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43oC to 127oC to identify the temperature compensation point and is observed at VGS = 0.55 V and ID = 3.86 × 10-6 A. Furthermore, the vital process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses reveal that, for sub -7 nm, the NSFET is a potential device for high performance and suitable for logic applications.

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References

  1. Zhang W, Fossum JG, Mathew L, Du Y (2005) Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans. Electron Devices 52(10):2198–2206

    Article  Google Scholar 

  2. Sreenivasulu VB, Narendar V (2021) Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length. AEU - International Journal of Electronics and Communications 137:153803

    Article  Google Scholar 

  3. Tayal S, Nandi A (2017) Study of 6T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET. Superlattices and Microstructures. https://doi.org/10.1016/j.spmi.2017.08.061

  4. Ghosh P, Bhowmick B (2020) Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis. Int J RF Microw Comput Aided Eng. 30(e22269)

  5. K. Baral, P.K. Singh, S. Kumar, S. Chander, S. Jit, Ultrathin body nanowire hetero dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability, Superlattice. Microst. 138 (2019), doi: https://doi.org/10.1016/j.spmi.2019.106364

  6. Narula V, Saini A, Agarwal M (2021) Correlation of Core Thickness and Core Doping with Gate & Spacer Dielectric in Rectangular Core Shell Double Gate Junctionless Transistor. IETE Journal of Research. https://doi.org/10.1080/03772063.2021.1946437

  7. Kumar B, Chaujar R (2021) Numerical Study of JAM-GS-GAA FinFET: A Fin Aspect Ratio Optimization for Upgraded Analog and Intermodulation Distortion Performance. Silicon. https://doi.org/10.1007/s12633-021-01395-8

  8. Sreenivasulu VB, Narendar V (2021) A Comprehensive Analysis of Junctionless Tri-gate (TG) FinFET Towards Low-power and High-frequency Applications at 5-nm Gate Length. Silicon

  9. Roy Barman K, Baishya S (2019) Performance analysis of vertical super-thin body (VSTB) FET and its characteristics in presence of noise. Appl. Phys. A 125:401. https://doi.org/10.1007/s00339-019-2682-x

    Article  CAS  Google Scholar 

  10. Barman KR, Baishya S (2021) An Insight into the DC and Analog/RF Response of a Junctionless Vertical Super-Thin Body FET towards High-K Gate Dielectrics. Silicon. https://doi.org/10.1007/s12633-021-01393-w

  11. Kale S, Chandu MS (2021) Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current. Silicon. https://doi.org/10.1007/s12633-020-00921-4

  12. Crupi G, Caddemi A, Schreurs DMM-P, Wiatr W, Mercha A (2011) Microwave noise modelling of FinFETs. Solid-State Electron. 56:18–22

    Article  CAS  Google Scholar 

  13. Singh R, Kaim S, MedhaShree R et al (2021) Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation. Silicon. https://doi.org/10.1007/s12633-021-01191-4

  14. Khalil Tamersit. Sub-10 nm junctionless carbon nanotube field-effect transistors with improved performance, AEU - International Journal of Electronics and Communications. 2020; 124:153354

  15. K. R. Barman and S. Baishya, "An Architectural Parametric Analysis for Vertical Super-Thin Body (VSTB) MOSFET with Double Material Gate (DMG)," TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), 2019, pp. 62-66, doi: https://doi.org/10.1109/TENCON.2019.8929531.

  16. Roy Barman K, Baishya S (2019) An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics. Appl. Phys. A 125:865. https://doi.org/10.1007/s00339-019-3165-9

    Article  CAS  Google Scholar 

  17. Barman KR, Baishya S (2021) Structural Optimization of a Junctionless VSTB FET to Improve its Electrical and Thermal Performance. IEEE Transactions on Nanotechnology 20:818–825. https://doi.org/10.1109/TNANO.2021.3119025

    Article  CAS  Google Scholar 

  18. Das D, Baishya S, Chakraborty U (2020) Impact of temperature on RF characteristics and electrical noise analysis of an L-shaped gate tunnel FET with hetero-stacked source configuration. Int J RF Microw Comput Aided Eng 30:e22310

    Article  Google Scholar 

  19. R. Saha, B. Bhowmick, S. Baishya, Study on impact of ferroelctric layer thickness on RF/analog and linearity parameters in ferroelctric-FinFET. Int J RF Microw Comput Aided Eng, (2021)

  20. X. He, J. Fronheiser, P. Zhao, Z. Hu, S. Uppal, X. Wu, Y. Hu, R. Sporer, L. Qin, R. Krishnan, E. M. Bazizi, R. Carter, K. Tabakman, A. K. Jha, H. Yu, O. Hu, D. Choi, J. G. Lee, S. B. Samavedam and D. K. Sohn, "Impact of aggressive ¦n width scaling on ¦nfet device characteristics," IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2017. DOI: https://doi.org/10.1109/IEDM.2017.8268427

  21. Katti G, DasGupta N, DasGupta A (2004) Threshold voltage model for mesaisolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson’s equation. IEEE Trans. Electron Devices 51:1169

    Article  CAS  Google Scholar 

  22. Kumar B, Chaujar R (2021) Analog and RF performance evaluation of Junctionless accumulation mode (JAM) gate stack gate allaround (GS-GAA) FinFET. Silicon. https://doi.org/10.1007/s12633-020-00910-7

  23. Gupta N, Kumar A, Chaujar R (2020) Design Considerations and Capacitance Dependent Parametric Assessment of Gate Metal Engineered SiNW MOSFET for ULSI Switching Applications. Silicon 12:1501–1510. https://doi.org/10.1007/s12633-019-00246-x

    Article  CAS  Google Scholar 

  24. Kumar, R and Kumar A. Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications. Appl. Phys. 2021; A 127, 26

  25. Rajiv Ranjan Thakur and Nidhi Chaturvedi, Design, Optimization, and Analyisis of Si and GAN Nanowire FETs for 3 nm Technology, Semicond. Sci. Technol. 36 2021 075013.

  26. Sanjay P, B. & Vohra, A. (2021) Effect of 3 nm gate length scaling in junctionless double surrounding gate SiNT MOSFET by using triple material gate engineering. Microsyst Technol.

  27. Sreenivasulu V, Narendar V (2021) Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications. ECS J. Solid State Sci. Technolo. 10:013008

    Article  Google Scholar 

  28. F. M. Buser, R. Ritzenthaler, H. Mertens, G. Eneman, A. Mocut and N. Horiguchi, "Performance Comparison of n-Type Si Nanosheets, and FinFETs by MC Device Simulation," IEEE Electron Device Lett., vol. 39, no. 11, p. 1628–1631, Nov 2018. DOI: https://doi.org/10.1109/LED.2018.2868379

  29. Jang D et al (June 2017) Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node. in IEEE Transactions on Electron Devices 64(6):2707–2713. https://doi.org/10.1109/TED.2017.2695455

    Article  CAS  Google Scholar 

  30. K. Kalna, D. Nagy, A. J. García-Loureiro and N. Seoane, "3D Schrödinger Equation Quantum Corrected Monte Carlo and Drift Diffusion Simulations of Stacked Nanosheet Gate-All-Around Transistor," IWCN, Wien: Institute for Microelectronics, TU Wien, May,2019, pp. 33-35.

  31. S. D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook and M. H. Na, "Performance Trade-offs in FinFET and Gate-All-Around Device Architectures for 7nm-node and Beyond," 2015 IEEE SOI-3DSubthreshold Microelectronics Technology United Conference (S3S), Rohnert Park, CA, USA, Oct. 2015. DOI: https://doi.org/10.1109/S3S.2015.7333521

  32. Lee B-H, Kang M-H, Ahn D-C, Park J-Y, Bang T, Jeon S-B, Hur J, Lee D, Choi Y-K (2015) Vertically integrated multiple nanowire field effect transistor. Nano Lett. 15:8056–8061

    Article  CAS  PubMed  Google Scholar 

  33. N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,” Proc. Symp. VLSI Technol., Jun. 2017, pp. 230–231, doi: 10.23919/VLSIT.2017.7998183.

  34. Barman, KR, Baishya, S. Study of enhanced DC and analog/radio frequency performance of a vertical super-thin body FET by high-k gate dielectrics. Int J RF Microw Comput Aided Eng. 2021;e22940. doi:10.1002/mmce.22940

  35. Kuheli Roy Barman, Srimanta Baishya, Improved electrical and RF performance of a junctionless vertical super-thin body (VSTB) FET by increased substrate doping, Materials Science in Semiconductor Processing, Volume 135, 2021,106100, ISSN 1369-8001, doi: 10.1016/j.mssp.2021.106100.

  36. Barman, KR, Baishya, S. The beneficial impact of a p–p+ junction on DC and analog/radio frequency performance of a vertical super-thin body FET. Int J RF Microw Comput Aided Eng. 2021;e22938. doi:10.1002/mmce.22938

  37. Bohr MT, Chau RS, Ghani T, Mistry K (Oct. 2007) The High-k Solution. in IEEE Spectrum 44(10):29–35. https://doi.org/10.1109/MSPEC.2007.4337663

    Article  Google Scholar 

  38. Zhang X, Connelly D, Takeuchi H, Hytha M, Mears RJ, Liu TK (Jan. 2017) Comparison of SOI Versus Bulk FinFET Technologies for 6T-SRAM Voltage Scaling at the 7-/8-nm Node. in IEEE Transactions on Electron Devices 64(1):329–332. https://doi.org/10.1109/TED.2016.2626397

    Article  CAS  Google Scholar 

  39. Jerry G (2010) Fossum. Zhenming Zhou, Leo Mathew, Bich-Yen Nguyen, SOI versus bulk-silicon nanoscale FinFETs, Solid-State Electronics 54(2):86–89, ISSN 0038-1101. https://doi.org/10.1016/j.sse.2009.12.002

    Article  CAS  Google Scholar 

  40. Genius, 3-D Device Simulator, Version1.9.0, Reference Manual, Cogenda, Singapore, 2008.

  41. Sreenivasulu V, Narendar V p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis. ECS J. Solid State Sci. Technolo. https://doi.org/10.1149/2162-8777/ac3bdf

  42. Sreenivasulu VB, Narendar V (2021) Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications. Silicon. https://doi.org/10.1007/s12633-021-01145-w

  43. Jegadheesan V, Sivasankaran K, Konar A (Apr. 2019) Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor. Mater. Sci. Semicond. Process. 93:188–195. https://doi.org/10.1016/j.mssp.2019.01.003

    Article  CAS  Google Scholar 

  44. Geppert L (Oct. 2002) The amazing vanishing transistor act. in IEEE Spectrum 39(10):28–33. https://doi.org/10.1109/MSPEC.2002.1038566

    Article  Google Scholar 

  45. Sreenivasulu VB, Narendar V (2021) Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling. Silicon. https://doi.org/10.1007/s12633-021-01471-z

  46. Min-Ju Ahn et al. Superior subthreshold characteristics of gate-all-around (GAA) p-type junctionless poly-Si nanowire transistor with ideal subthreshold slope. 2020 Jpn. J. Appl. Phys. in press doi: 10.35848/1347-4065/ab9e7d

  47. Sreenivasulu VB, Narendar V (2021) Design insights into RF/analog and linearity/distortion of spacer engineered multi-fin SOI FET for terahertz applications. Int J RF Microw Comput Aided Eng. 31(12):e22875. https://doi.org/10.1002/mmce.22875

    Article  Google Scholar 

  48. International technology roadmap for semiconductors (ITRS), Semicond. Ind. Assoc. 1 (2015).

  49. Barman KR, Baishya S (2021) Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET. Silicon 13:1993–2002. https://doi.org/10.1007/s12633-020-00561-8

    Article  CAS  Google Scholar 

  50. Kumar B, Chaujar R (2021) TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance. Silicon 13:3741–3753. https://doi.org/10.1007/s12633-021-01040-4

    Article  CAS  Google Scholar 

  51. Wong HSP, Frank DJ, Solomon PM, Wann CHJ, Welser JJ (1999) Nanoscale CMOS. P. IEEE 87(4):537–570. https://doi.org/10.1109/5.752515

    Article  Google Scholar 

  52. Toan HLM, Singh SS, Maity SK (2021) Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET. Silicon 13:2077–2087. https://doi.org/10.1007/s12633-020-00615-x

    Article  CAS  Google Scholar 

  53. V. Bharath Sreenivasulu, Vadthiya Narendar, Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes, Microelectronics Journal, 116, (2021),105214,

  54. Hou Y-T, Ming-Fu L, Low T, Kwong D-L (2004) Metal gate work function engineering on gate leakage of MOSFETs. IEEE Transactions on Electron Devices. 51(11):1783–1789

    Article  CAS  Google Scholar 

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Acknowledgements

The authors thank to the department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.

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  1. Department of Electronics & communication Engineering, National Institute of Technology Warangal, Warangal, Telangana, 506004, India

    N. Aruna Kumari & P. Prithvi

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  1. N. Aruna Kumari
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  2. P. Prithvi
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N. Aruna Kumari: Methodology, Writing- Original draft preparation, Formal Analysis, Software, Investigation, Visualization, Data Curation.

P. Prithvi: Supervision.

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Correspondence to N. Aruna Kumari.

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Kumari, N.A., Prithvi, P. Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters. Silicon 14, 9821–9831 (2022). https://doi.org/10.1007/s12633-022-01695-7

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