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Geometrical Variability Impact on the Performance of Sub - 3 nm Gate-All-Around Stacked Nanosheet FET

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Abstract

To meet the scaling targets and continue with Moore’s Law, the transition from FinFET to Gate-All-Around (GAA) nanosheet Field Effect Transistors (FETs) is the necessity for low-power to high-performance applications in upcoming nodes. In this work, we benchmark nanosheet FET against FinFET of comparable dimensions. Due to increased effective width, stacked nanosheet FET offers improved DC and analog/RF performance over multi-fin FinFET. The impact of geometrical parameter variations on the performance of stacked Si nanosheet FET is investigated for sub-3 nm technology node. We have considered nanosheet thickness (NST), nanosheet width (NSW), number of channels and oxide thickness (tox) as the sources of variability. The simulation carried out on Genius TCAD device simulator reports that higher NST, higher NSW, more number of channels and thinner oxide results in improved device driving capability, ON-current (Ion), transconductance (gm), intrinsic delay and cut-off frequency (ft). OFF-current (Ioff), ON-current to OFF-current ratio (Ion/Ioff), immunity against short channel effects (SCEs) and gate capacitance (Cgg) can be improved using lower NST, lower NSW, lesser number of channels and thinner oxide. However, threshold voltage (Vth) roll-off is more pronounced for thinner and narrower sheets with a thin oxide.

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Acknowledgements

The authors thank to the department of Electronics Engineering, J.C.Bose University of Scienceand Technology, YMCA for providing the TCAD Tools.

Funding

The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

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Authors and Affiliations

  1. Department of Electronics Engineering, J.C.Bose University of Science and Technology, YMCA, Sector 6, Faridabad, 121006, Haryana, India

    Nisha Yadav & Sunil Jadav

  2. Department of Electronics and Communication Engineering, National Institute of Technology, Kurukshetra, 136119, Haryana, India

    Gaurav Saini

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  1. Nisha Yadav
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  2. Sunil Jadav
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  3. Gaurav Saini
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Contributions

All the works (Conceptualization, Methodology, Writing Original Draft, Software, Validation and Investigation, Formal analysis, Resources, Data curation, Writing Review and Editing) in this paper have done together by Nisha Yadav, Sunil Jadav and Gaurav Saini. All authors read and approved the final manuscript.

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Correspondence to Nisha Yadav.

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Yadav, N., Jadav, S. & Saini, G. Geometrical Variability Impact on the Performance of Sub - 3 nm Gate-All-Around Stacked Nanosheet FET. Silicon 14, 10681–10693 (2022). https://doi.org/10.1007/s12633-022-01770-z

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