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Design and Analysis of Gate Stack Silicon-on-Insulator Nanosheet FET for Low Power Applications

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Abstract

Since the introduction of fast integrated circuits, semiconductor manufacturers have concentrated their efforts on reducing the size of transistors. Increased working frequencies (shorter transistors) and decreased power consumption are the goals of circuit designers working on large-scale production costs (with the lowering of supply voltage). Short channel effects (SCEs) are a side effect of transistor shrinkage. While reducing gate oxide thickness in downscaled devices, gate stack engineering is an approach that directs to an increase in leakage current (quantum tunnelling effect). SiO2's application as gate insulation is anticipated to result in a gradual increase in tunnelling leakage current. As a result, the market has witnessed an increase in innovative device architectures as Fin field effect transistors (FinFET). Nanosheets is a cutting-edge method that overcomes FinFET's constraints. In this study, sub-nm junction-less Gate Stack Silicon-on-Insulator (SOI) nanosheet FinFETs (NS FinFET) for both low and high levels of doping are examined. From doping concentration (ND) range of 1016 cm-3 to 1019 cm-3, the comprehensive DC performance evaluation is examined, including transfer characteristics, output characteristics, subthreshold swing (SS), drain induced barrier lowering (DIBL), and ION/IOFF ratio. The proposed Junction less FinFET produces better switching characteristics with IOFF getting less than nA for all the doping ranges. Furthermore, dynamic power and power consumption of the proposed JLFET is investigated. It shows paradigm shift for the semiconductor industries for low-power and high-performance applications at sub-nm region.

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Acknowledgements

The authors acknowledge the Device Simulation Laboratory in Department of Electronics and Telecommunication set up through TEQIP-3 grant at Parala Maharaja Engineering College, Berhampur, India for providing all necessary facilities to carry out the research work.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Excel Engineering College, Namakkal, India

    R. Yuvaraj

  2. Department of Electronics and Communication Engineering, Gnanamani College of Technology, Namakkal, Tamil Nadu, 637018, India

    Anand Karuppannan

  3. Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, 500090, India

    Asisa Kumar Panigrahy

  4. Department of ETC, Parala Maharaja Engineering College, Berhampur, 761003, Odisha, India

    Raghunandan Swain

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  1. R. Yuvaraj
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  2. Anand Karuppannan
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  3. Asisa Kumar Panigrahy
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  4. Raghunandan Swain
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Contributions

Asisa Kumar Panigrahy, Raghunandan Swain: Conceptualization; R. Yuvaraj, Asisa Kumar Panigrahy, Raghunandan Swain: investigation; Anand Karuppannan, Raghunandan Swain: resources; R. Yuvaraj, Anand Karuppannan, Asisa Kumar Panigrahy, Raghunandan Swain: data curation; Asisa Kumar Panigrahy, Raghunandan Swain: writing—original draft preparation; Asisa Kumar Panigrahy, Raghunandan Swain: writing—review and editing; R. Yuvaraj, Anand Karuppannan, Asisa Kumar Panigrahy, Raghunandan Swain: visualization; Asisa Kumar Panigrahy, Raghunandan Swain: supervision.

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Correspondence to Asisa Kumar Panigrahy.

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Yuvaraj, R., Karuppannan, A., Panigrahy, A.K. et al. Design and Analysis of Gate Stack Silicon-on-Insulator Nanosheet FET for Low Power Applications. Silicon 15, 1739–1746 (2023). https://doi.org/10.1007/s12633-022-02137-0

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  • DOI: https://doi.org/10.1007/s12633-022-02137-0

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