Abstract
In this paper, we comprehensively assess the unique features, feasibility and limitations of dual material gate fin field effect transistor for tuning the threshold voltage in nanoscale regime. The device performance is considerably improved via employing a gate configuration having an adjustable workfunction values, enabling operation of the device at a selected threshold voltage. The proposed structure contains a high workfunction gate material at the source side as well as a low workfunction gate material at the drain side, which screens the drain lateral electric field. The simulation results specify the superiority of dual material structure in terms of adjusting the threshold voltage, suppression of short channel effects due to the creation of a step in the surface channel potential profile and improvement of on/off current ratio. Impact of critical design parameters on the feasibility of dual material structure are thoroughly investigated and statistical analysis has been carried out to assess the sensitivity of device main electrical measures with respect to the variation of design parameters. The fin width is a fundamental design parameter which degrades the feasibility of dual material structure in nanoscale regime. The results demonstrate that for long channel devices, dual material structure exhibited modified electrical performance. However, it is seen that for extremely scaled devices with gate length below 10nm, single material gate material with high workfunction is the appropriate approach for efficient device performance.
Similar content being viewed by others
Data Availability
In case of no conflict of interest, any materials and data that are reasonably requested by others are available to members of the scientific community for noncommercial purposes.
Code Availability
In case of no conflict of interest, the code that are reasonably requested by others are available to members of the scientific community for noncommercial purposes.
References
Xie Q, Wang Z, Taur Y (2017) Analysis of short-channel effects in junctionless DG MOSFETs. IEEE Trans Electron Devices 64(8):3511–3514
Banerjee P, Sarkar SK (2017)3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects. J Comput Electron 16(3):631–639
Narendar V, Narware P, Bheemudu V, Sunitha B (2020) Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane(DMBSGP) FinFET. Silicon 12(10):2283–2291
Jha S, Choudhary SK (2020) A comparative analysis of the short-channel effects of double-gate, tri-gate and gate-all-around MOSFETs. Int J Nanopart 12(1–2):112–121
Adenekan O, Holland P, Kalna K (2018) Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications. Microelectron J 81:94–100
Ojha A, Mohapatra NR (2019) A computationally efficient quantum-corrected Poisson solver for accurate device simulation of multi-gate FETs. Solid-State Electron 160:107625
Razavieh A, Zeitzoff P, Nowak EJ (2019) Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans Nanotechnol 18:999–1004
Seo M, Kang MH, Jeon SB, Bae H, Hur J, Jang BC, Yun S, Cho S, Kim WK, Kim MS, Hwang KM (2018) First demonstration of a logic-process compatible junctionless ferroelectric FinFET synapse for neuromorphic applications. IEEE Electron Device Lett 39(9):1445–1448
Amrouch H, Pahwa G, Gaidhane AD, Dabhi CK, Klemme F, Prakash O, Chauhan YS (2020) Impact of variability on processor performance in negative capacitance finfet technology. IEEE Trans Circuits Syst I Regul Pap 67(9):3127–3137
Saha R, Bhowmick B, Baishya S (2018) Temperature effect on RF/analog and linearity parameters in DMG FinFET. Appl Phys A 124(9):1–10
Ahangari Z, Asadi E, Hosseini SA (2022) Performance optimization and sensitivity analysis of junctionless FinFET with asymmetric doping profile. J Nanoanal 7(4):310–320
Darwin S, Samuel TA (2020) A holistic approach on Junctionless dual material double gate (DMDG) MOSFET with high k gate stack for low power digital applications. Silicon 12(2):393–403
Chakrabarti H, Maity R, Maity NP (2019) Analysis of surface potential for dual-material-double-gate MOSFET based on modeling and simulation. Microsyst Technol 25(12):4675–4684
Banerjee P, Sarkar SK (2018) Comprehensive analysis of subthreshold short channel behavior of a dual-material gate strained trapezoidal FinFET. Superlattices Microstruct 117:527–537
Saha R, Bhowmick B, Baishya S (2019) Quantum modeling of threshold voltage in Ge dual material gate (DMG) FinFET. Solid-State Electron 159:129–134
(2015) Manual ATLASU. Silvaco International, Santa Clara
Han JW, Choi BJ, Yang JJ, Moon DI, Choi YK, Williams RS, Meyyappan M (2013) A replacement of high-k process for CMOS transistor by atomic layer deposition. Semicond Sci Technol 28(8):082003
Huang SE, Yu CL, Su P (2019) Investigation of Fin-width sensitivity of threshold voltage for InGaAs and Si negative-capacitance FinFETs considering quantum-confinement effect. IEEE Trans Electron Devices 66(6):2538–2543
Esqueda IS (2017) Confinement effects on radiation response of SOI FinFETs at the scaling limit. IEEE Electron Device Lett 38(3):306–309
Vimala P, Samuel TA (2020) TCAD simulation study of single-, double-, and triple-material gate engineered trigate FinFETs. Semiconductors 54(4):501–505
Hong Y, Guo Y, Yang H, Yao J, Zhang J, Ji X (2014) A novel Bulk-FinFET with dual-material gate. In 2014 12th IEEE international conference on solid-state and integrated circuit technology (ICSICT). IEEE, New York, pp 1-3
Daga M, Mishra GP (2021) Subthreshold performance improvement of underlapped FinFET using workfunction modulated dual-metal gate technique. Silicon 13(5):1541–1548
Hirpara Y, Saha R (2021) Analysis on DC and RF/analog performance in Multifin-FinFET for wide variation in work function of metal gate. Silicon 13(1):73–77
Daga M, Mishra GP (2021) Improvement in electrostatic effeciency using workfunction modulated dual metal gate FinFET. Mater Today: Proc 43:3443-3446
Author information
Authors and Affiliations
Contributions
All authors discussed, simulated the results and contributed to the final manuscript.
Corresponding author
Ethics declarations
Conflicts of Interest/Competing Interests
The authors declare that there is no conflict of interest.
Ethics Approval
This research is a simulation study and there is no ethics to declare.
Consent to Participate
This research is a simulation study and there is no “Consent to participate” to declare- Not applicable.
Consent for Publication
I, Zahra Ahangari and on behalf of the other author Farzad Mehrdad, give my consent for the publication of identifiable details, which can include figures and details within the text and the whole manuscript to be published in the journal of Silicon.
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Mehrdad, F., Ahangari, Z. Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering. Silicon 14, 7567–7576 (2022). https://doi.org/10.1007/s12633-021-01494-6
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12633-021-01494-6