Abstract
Concerned work is solely dedicated to the optimized characteristics of Nanoscale vacuum channel TF (Truncated fin)-FinFET at gate length of 7 nm. NVCTF-FinFET has its own benefit, due to high immune to noise and temperature as compared to TF-FinFET. The working of device stood perfectly well in case of NVCTF-FinFET. When tested, we end up with 3 times less current variation w.r.t temperature, 3 times more efficiency, 104 times more amplifying power analysed at corresponding peak values. These results evident the performance enhancement of NVCTF-FinFET, if seen from analog point of view. When studied from the perspective of linearity for RFIC designs, we end up with enhancement in some figure of merits such as 3.5 times in 1-dB compression point, 4 times more IP3, 102 times in HD3 and around 105 times in IMD3 at corresponding peak values. As NVCTF-FinFET provided descent switching ratio and Vth at input voltage (<2 V), which could lead these transistors beyond Moore’s law. These simulation difference ultimately made NVCTF-FinFET, a significant candidate to high speed and noise reduction System on chip (SOCs) operations in outer space.
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References
Boukortt N, Patanè S, Crupi G (2019) 3D investigation of 8-nm tapered n-FinFET model. Silicon 12:19–20. https://doi.org/10.1007/s12633-019-00253-y
Kashyap MP, Chaujar R (2020) "temperature investigation of a novel 3nm TF-bulk FinFET for improved performance," 2020 IEEE 20th international conference on nanotechnology (IEEE-NANO). Montreal, QC, pp 382–387. https://doi.org/10.1109/NANO47656.2020.9183594
Kumar A, Tripathi MM, Chaujar R (2017) Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications. Microsystem Technol 23(12):5867–5874. https://doi.org/10.1007/s00542-017-3348-2
Kumar A, Gupta N, Chaujar R (2016) Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour. Microsyst Technol 22(11):2665–2671. https://doi.org/10.1007/s00542-015-2554-z
Yu E, Heo K, Cho S (2018) Characterization and optimization of inverted-T FinFET under Nanoscale dimensions. IEEE Trans Electron Devices 65(8):3521–3527. https://doi.org/10.1109/TED.2018.2846478
Sachid AB, Manoj CR, Sharma DK, Ramgopal Rao V (2008) Gate fringe-induced barrier lowering in Underlap FinFET structures and its optimization. IEEE Electron Device Letters 29(1):128–130. https://doi.org/10.1109/LED.2007.911974
Han MH, Chang CY, Bin Chen H, Wu JJ, Cheng YC, Wu YC (2013) Performance comparison between bulk and SOI junctionless transistors. IEEE Electron Device Lett 34(2):169–171. https://doi.org/10.1109/LED.2012.2231395
Huang WT, Li Y (2015) Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants. Nanoscale Res Lett 10(1):1–8. https://doi.org/10.1186/s11671-015-0739-0
Zheng P, Liao Y, Damrongplasit N, Chiang M-H, Liu K, Tsu-Jae (2014) Variation-aware comparative study of 10-nm GAA versus FinFET 6-T SRAM performance and yield. IEEE Trans Electron Devices 61(12):3949–3954. https://doi.org/10.1109/TED.2014.2360351
Kashyap MP, Chaujar R (2020) Gate oxide variability analysis of a novel 3 nm truncated fin–FinFET for high circuitry performance. Silicon. https://doi.org/10.1007/s12633-020-00734-5
Kranti A, Armstrong GA (2007) Design and optimization of FinFETs for ultra-low-voltage analog applications. IEEE Trans Electron Devices 54(12):3308–3316. https://doi.org/10.1109/TED.2007.908596
Liu C, Zheng F, Sun Y, Li X, Shi Y (2017) Novel tri-independent-gate FinFET for multi-current modes control. Superlattice Microst 109:374–381. https://doi.org/10.1016/j.spmi.2017.05.025
Sachid AB, Chen MC, Hu C (2016) FinFET with high-κ spacers for improved Drive current. IEEE Electron Device Lett 37(7):835–838. https://doi.org/10.1109/LED.2016.2572664
Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (Feb. 2019) An impact ionization MOSFET with reduced breakdown voltage based on Back-gate misalignment. IEEE Trans Electron Devices 66(2):868–875. https://doi.org/10.1109/TED.2018.2887168
ITRS 2.0 Publication, “International Technology Roadmap for Semiconductors, 2015,” Available online at http://www.itrs2.net/
PH Drive, S. Clara, Atlas User’s Manual, Device Structure Editing and Simulation Software; 2017. Pp. 1–1715. Available: www.silvaco.com
Han J-W, Moon D-I, Meyyappan M (2017) Nanoscale Vacuum Channel Transistors. Nano Letters 17(4):2146–2151. https://doi.org/10.1021/acs.nanolett.6b04363
Ghosh P, Haldar S, Gupta RS, Gupta M (2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. Electron Devices IEEE Trans 59:3263–3268. https://doi.org/10.1109/TED.2012.2219537
Ellis RK (1982) Fowler-Nordheim emission from non-planar surfaces. IEEE Electron Device Letters 3(11):330–332. https://doi.org/10.1109/EDL.1982.25590
Forbes RG (1999) Refining the application of Fowler–Nordheim theory. Ultramicroscopy 79(1–4):11–23. https://doi.org/10.1016/S0304-3991(99)00097-2
Lenzlinger M, Snow EH (1968) Fowler-Nordheim tunneling into thermally grown SiO2. IEEE Trans Electron Devices 15(9):686–686. https://doi.org/10.1109/T-ED.1968.16430
Forbes R, Fischer A Mousa M (2012) Improved approach to Fowler-Nordheim plot analysis J Vacuum Sci Technol B vol 31. DOI: https://doi.org/10.1116/1.4765080
Xu J, Qin Y, Shi Y, Shi Y, Yang Y, Zhang X (2020) Design and circuit simulation of Nanoscale Vacuum Channel transistor. Nanoscale Advances 2:3582–3587. https://doi.org/10.1039/D0NA00442A
Sachid AB, Chen MC, Hu C (2017) Bulk FinFET with low-κ spacers for continued scaling. IEEE Trans Electron Devices 64(4):1861–1864. https://doi.org/10.1109/TED.2017.2664798
Ana F, Hakim N-U-D (2011) Gate Workfunction engineering for deep sub-Micron MOSFET’s: motivation, Features and Challenges. Electron Commun Japan (Part III Fundamental Electronic Science) 2:29–35
Erben E, Hempel K, Triyoso D (2018) Work function setting in high-k metal gate devices, complementary metal oxide semiconductor. Kim Ho Yeap and Humaira Nisar, IntechOpen. https://doi.org/10.5772/intechopen.783
Kang T, Yang Y, Chien F (2014) Poly Si nanowire thin film transistors with vacuum gap design. IEEE Trans Electron Devices 61(6):2113–2118. https://doi.org/10.1109/TED.2014.2318706
Kang S, Choi B, Kim B (2003) Linearity analysis of CMOS for RF application. Microwave Theory and Techniques. IEEE Trans 51:972–977. https://doi.org/10.1109/TMTT.2003.808709
Han J-W, Oh J, Meyyappan M (2012) Vacuum nanoelectronics: Back to the future? Gate insulated nanoscale vacuum channel transistor. Appl Phys Letters. 100. https://doi.org/10.1063/1.4717751
Garg N, Pratap Y, Gupta M, Kabra S (2020) Reliability assessment of GaAs/Al2O3 Junctionless FinFET in the presence of interfacial layer defects and radiations. IEEE Trans Device Mater Reliabil 20(2):452–458. https://doi.org/10.1109/TDMR.2020.2991662
Ballabio A, Bietti S, Scaccabarozzi A, Esposito L, Gurioli M, Isella G, Sanguinetti S (2019) GaAs epilayers grown on patterned (001) silicon substrates via suspended Ge layers. Nature Scientific Reports. DOI: 9. https://doi.org/10.1038/s41598-019-53949-x
Smith AH (1949) Temperature Dependence of the Work Function of Semiconductors. Phys Rev 75(6):953–959. https://doi.org/10.1103/PhysRev.75.953
Kumar A, Tiwari B, Singh S, Mohan Tripathi M, Chaujar R (2018) Radiation analysis of N-channel TGRC-MOSFET: an X-ray dosimeter. IEEE Trans Electron Devices 65(11):5014–5020. https://doi.org/10.1109/TED.2018.2869536
Lima L, Moreira M, Cioldin F, Diniz JA, Doi I, Pavanello M, Claeys C, Martino JA (2010) Tantalum nitride as promising gate electrode for MOS technology. ECS Trans 31:319–325. https://doi.org/10.1149/1.3474175
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All the authors would like to show the extreme regards to Microelectronics Research Laboratory, Department of Applied Physics, Delhi Technological University, for supporting this research work.
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The authors are grateful to Microelectronics Research Laboratory, Department of Applied Physics, Delhi Technological University for supporting this research work. However, there has been ‘no funding’ grants from the organization.
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All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by Mridul Prakash Kashyap, Sanmveg Saini and Rishu Chaujar. The first draft of the manuscript was written by Mridul Prakash Kashyap and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.
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Kashyap, M.P., Saini, S. & Chaujar, R. Analysis of a Novel Nanoscale Vacuum Channel TF-FinFET. Silicon 13, 3257–3269 (2021). https://doi.org/10.1007/s12633-021-01103-6
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DOI: https://doi.org/10.1007/s12633-021-01103-6