3D Investigation of 8-nm Tapered n-FinFET Model

Abstract

The miniaturization has become a key word for advanced integrated circuits over the last few years. It is within this context that the fin field effect transistor (FinFET) has appeared as a suitable technology to enable in every single chip to contain more million transistors. This paper proposes a numerical investigation of the influence of the gate length, drain/source doping concentrations, and gate work function on the output properties of 3D tapered FinFET technology by using Silvaco TCAD tools. The simulation results show that decreasing the gate length from 14 nm to 6 nm, the leakage current enhances dramatically and increasing the metal gate work function from 5.33 eV to 5.70 eV has affected transistor response time and the on-current, but in parallel, the leakage current increase affecting the transistor efficiency. The subthreshold slope (SS) and transconductance (g_m) are quite constant for all work function levels. This variation leads to determine the optimal metal gate work function of about 4.50 eV. The paper reports recent findings and some guidelines to achieve the following results: a threshold voltage (V_th) of 0.216 V, a subthreshold slope of 68.54 mV/dec, a transconductance of 315.7 μA/V, an on-current (I_on) of 103.75 μA, and an off-current (I_off) of 2.51 nA with a fixed gate length (L_g) of 8 nm, a top fin-width (F_WT) of 3 nm, a bottom fin-width (F_WB) of 6 nm, and a fin-height (F_H) of 50 nm, which are close to those reported in other research studies.