Abstract
For Ultra Large-Scale Integration (ULSI), the most promising device is multi gate Fin Field Effect Transistor (FinFET), as it offers reduced leakage current and better short channel performance. Modern design methodologies for 5 nm node NMOS FinFET transistors are examined in this paper to realize low power and low off state current (Ioff) needs. Changing the punch through stop implant dose, source and drain junction placement, gate work function, Drain Induced Barrier Lowering (DIBL), and sub-threshold slope in combination with cut-in voltage yields the Ioff and Ion (on state current). Source drain expansion design, Fin doping concentration, and gate work function selection are exploited such that a FinFET device provides the requirements of low power and ultra-low power transistors.
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Acknowledgements
The authors are thankful to Velalar College of Engineering and Technology, Erode, Tamil Nadu-638012. India for their cooperation and support during this research work.
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M Parimala Devi, and Velnath Ravanan: Conceptualization; M Parimala Devi, and Velnath Ravanan: investigation; M Parimala Devi, Velnath Ravanan, S Kanithan, and N A Vignesh : resources; M Parimala Devi, Velnath Ravanan, S Kanithan, and N A Vignesh: data curation; M Parimala Devi, Velnath Ravanan, S Kanithan, and N A Vignesh : writing—original draft preparation; M Parimala Devi, Velnath Ravanan, S Kanithan, and N A Vignesh: writing—review and editing; M Parimala Devi, Velnath Ravanan, S Kanithan, and N A Vignesh: visualization; M Parimala Devi, and Velnath Ravanan: supervision.
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Devi, M.P., Ravanan, V., Kanithan, S. et al. Performance Evaluation of FinFET Device Under Nanometer Regime for Ultra-low Power Applications. Silicon 14, 5745–5750 (2022). https://doi.org/10.1007/s12633-022-01772-x
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DOI: https://doi.org/10.1007/s12633-022-01772-x