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A Novel Self-Aligned Dopingless Symmetric Tunnel Field Effect Transistor (DL-STFET): A Process Variations Tolerant Design

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Abstract

This work reports a novel device structure, dopingless heterojunction symmetric tunnel field effect transistor (DL-STFET), based on the work-function engineering. For realizing dopingless P+-N-P+ structure a metal with workfunction as 4.7 eV is deployed as source as well as drain electrode. This metal results in induced P+ germanium regions for the source and drain implementation. The symmetric structure of the device obviates the inherent technical drawbacks of asymmetric P+-I-N+ TFET structure that does not support bidirectional current flow and results in area penalty in layout design. As our device structure offers bidirectional current flow across germanium source, silicon channel, and germanium drain region. This in turn makes logic designing easier and it guarantees its integration with conventional CMOS technology. To improvise the device switching behaviour silicon pad is also employed below source and drain regions. Here, using exhaustive calibrated 2D TCAD simulation analysis demonstrates sub-threshold slope (SS) approximately as 59 mV/decade. Further, as the device structure does not require physical doping it is expected to exhibit immunity towards random dopant fluctuation (RDFs) and trap assisted tunnelling (TAT). Moreover, easy fabrication flow for DL-STFET because of the absence of doping and ion implantation/annealing cuts the thermal budget for the fabrication of the device as well. This device can be a strong candidate for ultra-low power integrated circuits with 0.5 V supply voltage.

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References

  1. Koswatta SO, Lundstrom MS, Nikonov DE (2009) Performance comparison between pin tunneling transistors and conventional MOSFETs. IEEE Trans Electron Devices 56(3):456–465

    Article  CAS  Google Scholar 

  2. Boucart K, Riess W, Ionescu AM (2009) Lateral strain profile as key technology booster for all-silicon tunnel FETs. IEEE Electron Device Lett 30(6):656–658

    Article  CAS  Google Scholar 

  3. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  CAS  Google Scholar 

  4. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field effect transistorsn(TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745

    Article  CAS  Google Scholar 

  5. Krishnamohan T, Kim D, Raghunathan S, Saraswat K (2008) Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and <60mV/dec subthreshold slope. IEEE International Electron Devices Meeting (pp 1–3)

  6. Saurabh S, Kumar MJ (2010) Novel attributes of a dual material gate nanoscale tunnel field effect transistor. IEEE Trans Electron Devices 58(2):404–410

    Article  Google Scholar 

  7. Choi WY, Song JY, Lee JD, Park YJ, Park BG (2005) 70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field effect transistors (TFETs). In: IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest, pp 955–958

  8. Ram MS, Abdi DB (2015) Dopingless PNPN tunnel FET with improved performance: design and analysis. Superlattice Microst 82:430–437

    Article  CAS  Google Scholar 

  9. Kim SH, Agarwal S, Jacobson ZA, Matheu P, Hu C, Liu TJK (2010) Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett 31(10):1107–1109

    Article  CAS  Google Scholar 

  10. Nam H, Cho MH, Shin C (2015) Symmetric tunnel field-effect transistor (S-TFET). Curr Appl Phys 15(2):71–77

    Article  Google Scholar 

  11. Kumar MJ, Nadda K (2012) Bipolar charge-plasma transistor: a novel three terminal device. IEEE Trans Electron Devices 59(4):962–967

    Article  CAS  Google Scholar 

  12. Ramaswamy S, Kumar MJ (2014) Junctionless impact ionization MOS: proposal and investigation. IEEE Trans Electron Devices 61(12):4295–4298

    Article  CAS  Google Scholar 

  13. Amin SI, Sarin RK (2015) Charge-plasma based dual-material and gate-stacked architecture of junctionless transistor for enhanced analog performance. Superlattice Microst 88:582–590

    Article  CAS  Google Scholar 

  14. Hueting RJ, Rajasekharan B, Salm C, Schmitz J (2008) The charge plasma PN diode. IEEE Electron Device Lett 29(12):1367–1369

    Article  Google Scholar 

  15. ATLAS (2015) User Manual. Silvaco International, Santa Clara

    Google Scholar 

  16. Kim SH, Kam H, Hu C, Liu TJK (2009) Germanium-source tunnel field effect transistors with record high ION/IOFF. Symposium on VLSI Technology, pp 178–179

  17. Abbassi SA, Bashir F, Loan SA, Alamoud ARM, Nizamuddin M, Rafat M (2016) Hetero gate material and dual oxide dopingless tunnel FET. In Proc. IMECS, pp 1–3

  18. Bashir F, Loan SA, Rafat M, Alamoud ARM, Abbasi SA (2015) A high performance gate engineered charge plasma based tunnel field effect transistor. J Comput Electron 14(2):477–485

    Article  CAS  Google Scholar 

  19. Lee H, Park S, Lee Y, Nam H, Shin C (2014) Random variation analysis and variation-aware design of symmetric tunnel field-effect transistor. IEEE Trans Electron Devices 62(6):1778–1783

    Google Scholar 

  20. Kumar MJ, Janardhanan S (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE Trans Electron Devices 60(10):3285–3290

    Article  CAS  Google Scholar 

  21. Rajasekharan B, Hueting RJ, Salm C, van Hemert T, Wolters RA, Schmitz J (2010) Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Lett 31(6):528–530

    Article  CAS  Google Scholar 

  22. Singh S, Kondekar PN (2014) Dopingless super-steep impact ionisation MOS (dopingless-IMOS) based on work-function engineering. Electronics Lett 50(12):888–889

    Article  CAS  Google Scholar 

  23. Anand S, Amin SI, Sarin RK (2016) Analog performance investigation of dual electrode based doping-less tunnel FET. J Comput Electronics 15(1):94–103

    Article  Google Scholar 

  24. Chauhan SS, Sharma N (2018) Impact of spacer-gate engineered Workfunction on the performance of Dopingless TFET. J Nanoelectron Optoelectron 13(8):1200–1203

    Article  CAS  Google Scholar 

  25. Singh S, Kondekar PN (2017) A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: process resilient design. J Comput Electron 16(3):685–695

    Article  CAS  Google Scholar 

  26. Singh S, Sinha R, Kondekar PN (2018) Impact of PZT gate-stack induced negative capacitance on analogue/RF figures-of-merits of electrostatically-doped ferroelectric Schottky-barrier tunnel FET. IET Circuits Devices Syst 13(4):435–441

    Article  Google Scholar 

  27. Damrongplasit N, Shin C, Kim SH, Vega RA, Liu TJK (2011) Study of random dopant fluctuation effects in germanium-source tunnel FETs. IEEE Trans Electron Devices 58(10):3541–3548

    Article  CAS  Google Scholar 

  28. Damrongplasit N, Kim SH, Liu TJK (2013) Study of random dopant fluctuation induced variability in the raised-Ge-source TFET. IEEE Electron Device Lett 34(2):184–186

    Article  CAS  Google Scholar 

  29. Jhaveri R, Nagavarapu V, Woo JC (2010) Effect of pocket doping and annealing schemes on the source-pocket tunnel field effect transistor. IEEE Trans Electron Devices 58(1):80–86

    Article  Google Scholar 

  30. Damrongplasit N, Kim SH, Liu TJK (2013) Study of random dopant fluctuation induced variability in the raised-Ge-source TFET. IEEE Electron Device Lett 34(2):184–186

    Article  CAS  Google Scholar 

  31. Hueting RJ, Rajasekharan B, Salm C, Schmitz J (2008) The charge plasma PN diode. IEEE Electron Device Lett 29(12):1367–1369

    Article  Google Scholar 

  32. Duan X, Zhang J, Wang S, Li Y, Xu S, Hao Y (2018) A high-performance gate engineered InGaN dopingless tunnel FET. IEEE Trans Electron Devices 65(3):1223–1229

    Article  CAS  Google Scholar 

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Acknowledgements

The authors are grateful to the National Institute of Technology, Jamshedpur, India for providing the computational resources.

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Correspondence to Kunal Singh.

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Priyadarshani, K.N., Singh, S. & Singh, K. A Novel Self-Aligned Dopingless Symmetric Tunnel Field Effect Transistor (DL-STFET): A Process Variations Tolerant Design. Silicon 14, 229–237 (2022). https://doi.org/10.1007/s12633-020-00804-8

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