Abstract
In recent times, the role of FINFET devices is increasing in the field of RF-IC design for realizing the high frequency circuits. As a result, high frequency characteristics including RF stability needs to be investigated carefully. Hence this work presents the impact of device geometrical and process parameter variations on the RF stability of 20 nm SELBOX Inverted-T Junctionless FINFET (SELBOX ITJLFET). The stability factor (K), critical frequency (fk) and its dependency on small signal parameters (SSP) are investigated by varying the device and process parameters like Gate Workfunction (GWF), fin height (Hfin), fin width (Wfin), Source underlap spacer length (LUS) and SELBOX length (LG). In addition, the relation between the bias and the stability factor of the device is also studied to identify the bias operating point in a stability perspective. From the simulation results, it is found that larger the SELBOX and LUS, lower the critical frequency and thereby making the device unconditionally stable at lower frequencies. Finally, an optimized design guideline is proposed, which makes the device suitable for high bandwidth applications.
Similar content being viewed by others
References
PeiqiXuan, J. Kedzierski, V. Subramanian, J. Bokor, Tsu-Jae King, and Chenming Hu, "60 nm planarized ultra-thin body solid phase epitaxy MOSFETs," 58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526), Denver, CO, USA, 2000, pp. 67–68
Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T (1987) Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Lett 8(9):410–412
Doyle BS, Datta S, Doczy M, Hareland S, Jin B, Kavalieros J, Linton T, Murthy A, Rios R, Chau R (2003) High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett 24(4):263–265
Yang B, Buddharaju KD, Teo SHG, Singh N, Lo GQ, Kwong DL (2008) Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electron Device Lett 29(7):791–794
Imenabadi RM, Saremi M, Vandenberghe WG (2017) A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance. IEEE Trans Electron Devices 64(11):4752–4758
Abadi RMI, Saremi M (2018) A resonant tunneling nanowire field-effect transistor with physical contractions: a negative differential resistance device for low power very large scale integration applications. J Electron Mater 47(2):1091–1098.6
C. M. Venkatesh and N. B Balamurugan (2019), "New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field-effect transistor", Superlattices and Microstructures -Elsevier (130),485–498, 10.1016/j.spmi.2019.05.016
Hu, Univ. Calif. (2011) https://people.eecs.berkeley.edu/∼hu/FinFET-and-other-New-Transistor-Tech-Hu.pdf
Saremi M, Afzali-Kusha A, Mohammadi S (2012) Ground plane fin-shaped field-effect transistor (GP-FinFET): a FinFET for low leakage power circuits. Microelectron Eng 95:74–82
Kranti A, Armstrong GA (2007) Design and optimization of FinFETs for ultra-low-voltage analog applications. IEEE Trans. Electron Devices 54(12):3308–3316
Subramanian V, Mercha A, Parvais B, Loo J, Gustin C, Dehan M, Collaert N, Jurczak M, Groeseneken G, Sansen W, Decoutere S (2007) Impact of fin width on digital and analog performances of n-FinFETs. Solid State Electron 51(4):551–559
Colinge JP (ed) (2008) FinFETs and other multi-gate transistors, vol 73. Springer, New York
Bohr, M., and Mistry, K., 2011. Intel’s revolutionary 22 nm transistor technology. Intel website
Zhang W, Fossum JG, Mathew L (2006) The ITFET: A Novel FinFET-Based Hybrid Device. IEEE Trans. Electron Devices 53:2335–2343
Mathew L, Fossum JG, NXP USA Inc (2008) Hybrid-FET and its application as SRAM. US Patent 7:470,951
L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, S. Bagchi, C. Parker, J. Vasek, D. Sing, R. Shimer, L. Prabhu, G. O. Workman, G. Ablen, Z. Shi, J. Saenz, B. Min, D. Burnett, B.-Y. Nguyen, J. Mogab, M. M. Chowdhury, W. Zhang, and J. G. Fossum, “Inverted-T channel FET (ITFET)—Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45 nm and beyond CMOS,” in IEDM Tech. Dig., Dec. 2005, pp. 731–734. (2006)
Pradhan, K. P., and P. K. Sahu. “Exploration of symmetric high-k spacer (SHS) hybrid FinFET for a high-performance application.” SuperlatticesMicrostruct90 (2016): 191–197
Pradhan, K. P., M. G. C. Andrade, and P. K. Sahu. “Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs.” SuperlatticesMicrostruct100 (2016): 335–341. https://doi.org/10.1016/j.spmi.2016.09.043 9
Pradhan KP, Sahu PK (2017) Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs. Mater Sci Semicond Process 57:185–189
Sachid AB, Chen MC, Hu C (2016) FinFETWith high-k spacers for improved drive current. IEEE Electron Device Lett 37(7):835–838
Narendar V, Narware P, Bheemudu V, Sunitha B (2019) Investigation of Short Channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET. Silicon. https://doi.org/10.1007/s12633-019-00322-2
Bha JKK, Priya PA, Joseph HB, Thiruvadigal DJ (2019) 10 nm TriGate high k UnderlapFinFETs: scaling effects and analog performance. Silicon 12:2111–2119. https://doi.org/10.1007/s12633-019-00299-y
Colinge, J.P., Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P., O'neill, B., Blake, A., White, M. and Kelleher, A.M., 2010. Nanowire transistors without junctions. Nat. Nanotechnol., 5(3), p.225
A. Kranti, C.-W. Lee, I. Ferain, R. Yu, N.D. Akhavan, P. Razavi, J. Colinge, Junctionless nanowire transistor; properties and design guidelines, in proceedings of the 34th European solid-state device research conference, IEEE 357–360, 2010)
Paz, B.C., Pavanello, M.A., Cassé, M., Barraud, S., Reimbold, G., Faynot, O., Avila-Herrera, F. and Cerdeira, A., From double to the triple gate: Modeling junctionless nanowire transistors. In EUROSOI-ULIS 2015: Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (pp. 5–8). IEEE. 2015
Han, Ming-Hung, Chun-Yen Chang, Hung-Bin Chen, Jia-Jiun Wu, Ya-Chi Cheng, and Yung-Chun Wu. “Performance comparison between bulk and SOI junctionless transistors.” IEEE Electron Device Lett 34, no. 2 (2013): 169–171
Lü WF, Dai L (2019) Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET. Microelectron J 84:54–58
Biswas K, Sarkar A, Sarkar CK (2017) Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs. IET Circuits Devices Syst 11(1):80–88
Bousari NB, Anvarifard MK, Haji-Nasiri S (2019) Benefitting from high-κ spacer engineering in Balistic triple-gate JunctionlessFinFET- a full quantum study. Silicon. https://doi.org/10.1007/s12633-019-00318
Tayal S, Nandi A (2017) Analog/RF performance analysis of channel engineered high-k gate-stack based junctionless trigate-FinFET. SuperlatticesMicrostruct 112:287–295
Biswas K, Sarkar A, Sarkar CK (2016) Impact of fin width scaling on RF/analog performance of junctionless accumulation-mode bulk FinFET. ACM J. Emerging Technol. Comput 12(4):36
Biswas K (2018) AngsumanSarkar, and Chandan Kumar Sarkar. "fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs.". Microsyst Technol 24(5):2317–2324
Manikandan S, Balamurugan NB, Samuel TSA (2019) Impact of uniform and non-uniform doping variations for ultrathin body junctionless FinFETs. Materials Science in Semiconductor Processing 104:104653
Vandana B, Patro BS, Das JK, Kaushik BK, Mohapatra SK (2018) Inverted ‘T’Junctionless FinFET (ITJL FinFET): Performance Estimation through Device Geometry Variation. ECS Journal of Solid State Science and Technology 7(4):Q52–Q59
Su JG, Wong SC, Chang CY (2002) An investigation on RF CMOS stability related to bias and scaling. Solid State Electron 46(4):451–458
Sivasankaran K, Mallick PS (2013) Stability performance of optimized symmetric DG-MOSFET. J.Semicond. 34(10):104001
Sivasankaran K, Mallick PS (2015) Impact of parameter fluctuations on RF stability performance of DG tunnel FET. J. Semicond 36(8):084001
Venkatesh, M., M. Suguna, and N. B. Balamurugan. "Influence of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET for Improved Analog/RF Performance." Silicon: 1–9. (2020)
Raju V, Sivasankaran K (2019) Impact of high k spacer on RF stability performance of double gate junctionless transistor. Int. J. Numer. Modell. Electron. Networks Devices Fields 32(1):e2481
Pon, A., Bhattacharyya, A., Padmanaban, B., and Ramesh, R., 2019. Optimization of the geometry of a charge plasma double-gate junctionless transistor for improved RF stability. J. Comput. Electron., pp.1–12
Sivasankaran, K., and P. S. Mallick. "Bias and geometry optimization of FinFET for RF stability performance." J. Comput. Electron.13, no. 1 (2014): 250–256
Jegadheesan V, Sivasankaran K (2017) RF stability performance of SOI junctionlessFinFET and impact of process variation. Microelectron J 59:15–21
Manikandan, S., and N. B. Balamurugan. "The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET." J Comput (2020): 1–9
Nelapati, R.P., K., S. Process Variation Study of SELBOX Inverted- T Junctionless FinFET for High-Performance Applications. Silicon (2019). 10.1007/s12633-019-00270
Rollett J (1962) Stability and power-gain invariants of linear two ports. IRE Trans. Circuit Theory 9(1):29–32
Sarkar A (2012) Aloke Kumar Das, Swapnadip De, and Chandan Kumar Sarkar. “Effect of gate engineering in double-gate MOSFETs for analog/RF applications”. Microelectron J 43(11):873–882
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Raju, V., PankajNelapati, R. & Sivasankaran, K. Impact of Device Geometrical Parameter Variation on RF Stability of SELBOX Inverted-T Junctionless FINFET. Silicon 13, 2605–2617 (2021). https://doi.org/10.1007/s12633-020-00616-w
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12633-020-00616-w