Abstract
Heterogeneous integration is a key driver within the field of advanced electronic packaging. The realization of tomorrow’s highly integrated electronic systems depends on the combination and compatibility of various integration technologies at the same hierarchy level. The adoption of novel bonding technologies for a cost-effective realization of multi-chiplet systems is a key aspect. Cu nanowire (NW) interconnects exhibit distinct advantages in terms of their scalability down to a few micrometers, the resulting joint properties and moderate demands with respect to the surface preparation, and the cleanliness of the bonding environment. No solder or flux is required for the bonding process, but the NW bumps still can compensate low height differences. The bonding process can be carried out near room temperature under ambient conditions. We demonstrate the technological possibility to integrate the Cu-NWs for a bump processing scheme including the Cu seed etching on 300 mm wafer for the first time. This paper focuses on the microstructure evaluation and the shear test of the formed Cu-NW interconnects fabricated under ambient conditions within a few seconds. The microstructure analysis shows the intact bonded interconnects and reveals high-resolution details of Cu-NWs. The shear strength of the formed interconnects varies between 4.6 MPa and 90.5 MPa depending on the bonding and annealing conditions. Overall, the results of this study highlight the potential of Cu-NW interconnects for future 3D heterogeneous system integration.
Similar content being viewed by others
Avoid common mistakes on your manuscript.
Introduction
Since the 1960s, the increase in both computing performance and functionality has relied on the integration of a greater number of components into an electronic system.1 In recent years, the further shrinkage of integrated circuit dimensions has been associated with exponentially increasing costs. Therefore, advanced packaging technologies continuously gain importance within the semiconductor industry.2 They enable the fabrication of novel, highly integrated systems at moderate cost of development. Consequently, the heterogeneous integration (HI) of several components into a single package is a key driver in advanced packaging.3 HI is based on the combination of chiplets fabricated by different suppliers and thus adopts several interconnect technologies at the same hierarchy level.
The cost-effective realization of 2.5D and 3D packages with a broad spectrum of interconnect dimensions will comprise different bonding technologies. Therefore, the application-specific challenges will range from design and materials to technological processes and subsequent reliability issues.
Ultrafine interconnects at pitches below 10 µm for very high input/output counts are typically realized by SiO2/Cu and SiCN/Cu hybrid bonding.4,5,6,7 However, this technology is associated with exceptional levels in terms of the surface preparation and the cleanliness of the bonding environment. Because of its high cost of ownership, the adoption of hybrid bonding for pitches greater than 10 µm is questionable when cost-friendly alternatives are available.
Lead-free soldering and solid–liquid interdiffusion (SLID) based on low melting metals such as Sn8,9,10 and In11,12 are typically used for applications with pitches down to 30 µm. A further interconnect size reduction is associated with phenomena related to increased surface diffusion in the solid state,13 sidewall wetting14 and reliability issues.15 Moreover, the use of solders results in an irreversible consumption of Cu.16
Techniques based on thermocompression bonding (TCB) of identical metals exhibit the potential to close the gap drawn by an economically questionable adoption of hybrid bonding and the technological challenges of downscaled pillar bumps. Among all TCB approaches, Cu–Cu17,18 and Au–Au19,20 are the most important. While the application of Au is expensive, the formation of Cu–Cu interconnects requires very high bonding pressures for long dwell times at temperatures above 200°C and purged environments to prevent the oxidation of the bonding surfaces.21,22,23 For a reduction of the required bonding temperature, the bonding pressure and the dwell time, the adoption of nanostructured bumps gained distinct interest within the recent years. Typical examples are nanoporous (NP) Cu sponges,24,25 Cu nanowires (NWs)26,27,28,29 and particle-based pastes.30,31,32 The adoption of Cu-NWs for the formation of monometallic interconnects is of particular interest since the fabrication process is compatible with 300 mm back-end-of-line (BEOL) processes.
In this study, we investigate Cu-NW bumps for the realization of scalable fine-pitch interconnects under ambient conditions. We report two schemes for the processing of the Cu-NW bumps: (1) with remaining Cu seed layer; (2) with a protection layer applied on the Cu-NW bumps prior to the Cu seed etching. The second scheme is reported for the first time and is an enabling key technology. The proposed solderless NW bonding technology combines the advantages of Cu–Cu TCB with respect to a formation of monometallic interconnects and those of soldering/SLID bonding with respect to ambient bonding conditions and surface requirements. NanoWired reported electrical resistance values of Cu-NW interconnections with wire diameters of 1 µm which are indistinguishable from those of pure Cu bar specimens.33 The first experimental results of fine-pitch NW bump formation and bonding were published by Fraunhofer IZM-ASSID.28,34 Our current study focuses on both the realization of Cu-NW interconnects at 55 µm pitch and their microstructural characterization using high-resolution electron microscopy and electron backscatter diffraction (EBSD) analysis.
Experimental Part
Sample Fabrication
The test sample fabrication was carried out at Fraunhofer IZM-ASSID (Moritzburg, Germany) and at NanoWired GmbH (Gernsheim, Germany) using 300 mm Si wafers. The terminal metal layers on these wafers consisted of sputtered Ti adhesion and Cu seed films followed by a patterned photoresist. The Cu-NWs were electroplated at a temperature below 50°C onto compact Cu bumps using a track-etched polycarbonate membrane with a specific open area of 30%. The specific open area is equivalent, with mean distances between two wires of 330 nm for wires with a diameter of 400 nm and 83 nm for wires with a diameter of 100 nm. Details of the NW plating process are given in.35 All fabricated wafers exhibit Cu-NW bumps at a pitch of 55 µm but differ in terms of the used mask design, i.e. the bump layout and diameters. The process flow and the detailed specifications of both designs used in this study are given in Fig. 1 and Table I, respectively. Wafers with design A exhibit Cu-NWs with a wire diameter of 400 nm at a mean length of approximately 6 µm. Those wires were deposited onto compact Cu bumps with a mean height of 10 µm and diameters of 25 µm (top die) and 35 µm (bottom die), respectively.
Neither the Ti adhesion layer nor the Cu seed layer was removed on wafers with design A. The standard wet etching processes used for microbump processing cause a complete removal of Cu-NWs as our pre-experiments revealed. The removal of the Ti and Cu layers was carried out for wafers with design B. In order to protect the NWs against the chemical attack during the wet etching of the Cu seed layer, the wafers require another lithographic patterning step. The protective layer application is the crucial and novel technology step implemented for the first time in our study. The obtained design B wafers feature bumps with a mean diameter of 10 µm and Cu-NWs with a diameter of 100 nm at a mean length of approximately 3 µm. The final singulation into dies with an edge length of 5.1 mm (design A), 10 mm (B, top die) and 22 mm (B, bottom die) was realized by blade dicing.
Figure 2 illustrates the typical clustering of 2–4 Cu-NWs irrespective of the NW diameter This phenomenon may be a result of the pore coalescence already present in the template or a direct coalescence of the NWs after template stripping.
Flip-Chip Bonding and Annealing
Using a Panasonic FCB-3 flip-chip bonding machine, top dies were bonded onto the bottom dies under ambient conditions at bonding temperatures (Tbond) of 50°C and 220°C according to the schematic of the bonding profile shown in Fig. 3. In order to ensure the removal of oxides on Cu-NWs, the dies were exposed to a formic acid-enriched N2 atmosphere at 250°C using a Pink Vadu 200 reflow oven approximately 2 h prior to the bonding process. The same oven was used for annealing of the prepared die-to-die (D2D) stacks in pure N2 after the bonding process. An overview of the bonding and annealing parameters is given in Table II. Therein, Fbond is the bonding force, Tbond is the bonding temperature, Tanneal is the annealing temperature and tanneal is annealing time.
Shear Test
The shear strength of prepared D2D stacks was determined using a XYZTEC Condor Sigma equipped with a 200 kgf load cell (sample series A1–A3) and a Dage 4000 bondtester equipped with a 100 kgf load cell. All tests were carried out at a shear height of 40 µm and a test speed below 50 µm/s.
Metallographic Preparation
Cross-sections of Cu-NW interconnects were prepared by filling of the gap between the top and bottom dies using a low-viscosity underfill at first. The subsequent revealing of the sample area of interest involved mechanical grinding and final polishing with abrasive papers and diamond suspensions, respectively. The final physical polishing was carried out by Ar ion beam milling using a Gatan Ilion II-697 system. Lamella preparation for transmission electron microscopy (TEM) was performed using focused ion beam (FIB) in a Zeiss Auriga FIB-SEM tool. The lamellae were lift-off with a Kleindiek micromanipulator tool.
Microstructural and Image Analysis
Scanning electron microscopy (SEM) for investigation of the cross-sections of bonded samples and the failure characteristics of as-sheared NW interconnects was carried out using a Zeiss Leo 1530 SEM operated at an accelerating voltage 10 kV. The detailed microstructural analysis of the formed NW interconnects involved scanning TEM using an FEI Titan G2 60-300 with Cs correction at 300 kV including a Super-X energy dispersive X-ray (EDX) detector for a high-resolution composition analysis. Crystal orientation analysis of the NWs was conducted by means of electron backscatter diffraction (EBSD) on a Zeiss Supra SEM equipped with an EDAX Trident EBSD camera. The NW filling factors of formed interconnects were determined by thresholding the area of compressed NWs in the overlying area between the compact portions of the top and bottom Cu bumps/pads using ImageJ software.36
Results and Discussion
Die Shear Strengths and Cross-Sections of Cu-NW Interconnects with 25 µm Diameter
Figure 4a shows the determined die shear strengths τd for samples bonded at 50°C and annealed according to profile codes A1, A2 and A3. The application of a bonding force of 150 N, equivalent to a minimum bonding pressure of approximately 35 MPa, results in an average shear strength of 4.63 MPa (A1). The annealing of as-bonded stacks without the application of pressure at 300°C for 1 h leads to an increase of τd by roughly 20% to 5.59 MPa (A2). An increase of Fbond to 450 N, equivalent with a minimum bonding pressure of approximately 104 MPa, leads to an increase of the average shear strength to almost 17 MPa (A3). The cross-section of an interconnect formed under such conditions is shown in Fig. 4c and reveals a noticeable densification of the NWs between both Cu pads in the bonding zone with NW filling factors in the range 45–60%. However, the cross-sections do not provide sufficient evidence of the formation of NW-NW interdiffusion contacts. In fact, the formed interconnects seem to form on a hook-and-loop fastener principle.
The as-sheared Cu-NW bumps from the top and bottom dies in Fig. 5 show no obvious indication of NW-NW interdiffusion during the bonding process or the subsequent annealing step. The NWs appear predominantly preserved in terms of their adhesion to the respective compact Cu pad they grew on as well as in terms of their dimensions. Overall, the appearances and the cross-section in Fig. 4c and the as-sheared NW bumps in Fig. 5 confirm the hook-and-loop fastener bonding principle.
Microstructural Analysis of Cu-NW Interconnects with 25 µm Diameter
A detailed microstructural analysis was carried out on Cu-NW interconnects prepared by profile A3. Figure 6b shows a high-angle annular dark-field (HAADF) STEM image of a lamellar section (detail A in subfigure a) with four highlighted areas of NW-NW contacts. Area 1 in Fig. 6f shows two NWs weakly adhered to each other. Areas 2–4 in subfigures c–e on the other hand exhibit a local coalescence between the touching NWs. The HAADF micrograph in Fig. 6i (detail B in Fig. 6a) shows coalesced NWs perpendicular to their wire axes. The shape of the cluster’s cross-section and the distinct presence of oxides at its surface, but not at any inner interface (see EDX mapping in Fig. 6j), indicate that these wires might have been already merged before the bonding process. Due to the conditions of the bonding and annealing processes (residual oxygen is always present in the annealing chamber, bonding is done in ambient air), the oxidation of Cu surfaces is typically expected to take place.37 The EDX mapping for oxygen of area 1 (Fig. 6g) shows no distinct oxide formation on the surfaces of both touching wires. This effect might be based on an encapsulation effect of the surrounding NW network. Therefore, the formation of surface oxides is most likely negligible between the cleaning process and the formation of the NW interconnects at 50°C.
The EBSD results of the bonded NW-NW area is shown in Fig. 7. This sample type is very challenging to prepare defect-free for the EBSD measurement because of the requirement of the electrically conductive underfill between the individual wires. The inverse pole figure map in Fig. 7b shows a charging effect on the sample surface. White arrows indicate the spots where the NWs grew based on the Cu grain orientation of the Cu pad. While the majority of the NWs consist of multiple grains along the wire axis, there are also numerous NWs exhibiting grain boundaries perpendicular to the wire axis (rectangles in Fig. 7b). Similar to the TEM results, the coalesced state of NWs created during the bonding process is not explicitly visible. However, we believe the locally increased number of wires with a nearly identical crystallographic orientation (circle in Fig. 7b) as an indication of partially coalesced NWs with contact areas outside of the prepared section of the sample. Further investigation is required in order to examine whether the Cu-NWs have a bamboo-type microstructure like other metallic NWs.
Die Shear Strengths and Cross-Sections of Cu-NW Interconnects with 10 µm Diameter
Figure 8 shows the determined die shear strengths τd for the samples bonded and annealed according to the profile codes B1, B2 and B3. These bonding conditions show significant improvement compared to Cu-NW interconnects with 25 µm diameter. The application of a bonding force of 450 N, equivalent with a minimum bonding pressure of approximately 177 MPa, at 50°C results in an average shear strength of 25.86 MPa (B1). An additional annealing of as-bonded stacks without the application of pressure at 300°C for 1 h leads to an increase of τd by roughly 25% to 32.3 MPa (B2). An increase of Tbond from 50°C to 220°C without an annealing step leads to a significant increase of τd by almost 180% to 71.6 MPa (B3). The maximum measured value of τd for D2D stacks prepared by profile B3 is 90.5 MPa. The cross-section of an interconnect formed according to profile B3 is shown in Fig. 8c, which reveals a high level of compactness in the bonding zone with NW filling factor above 80%.
The as-sheared top die and bottom die bumps of Cu-NW interconnects formed at 450 N/50°C (profile B1, NW diameter of 100 nm) in Fig. 9a and b show shear failure behavior similar to the interconnects formed with 400 nm diameter NWs (design A): the wires show no signs of plastic flow. Consequently, the interconnect formation appears to be based on the hook-and-loop fastener principle. The shear failure behavior of interconnects formed at 450 N/220°C (profile B3) distinctly differs from those prepared at 50°C. Almost every interconnect exhibits shear failure outside the bonding zone of the NWs as exemplary shown in Fig. 9c. Consequently, the NW interconnect itself is not the mechanically weakest link in the system but rather the adhesion of the electroplated compact Cu pad on the under bump metallization or the adhesion of the wire bases on the Cu pad.
Summary and Conclusion
The fabrication of Cu–Cu fine-pitch interconnects at ambient conditions attracts high industrial interest for enabling the cost-effective realization of future highly integrated heterogeneous systems. In our current study, we report the following for the first time:
-
The realization of fine-pitch Cu-NW bumps with a diameter below 25 µm on 300 mm wafer level using fully compatible back-end-of-line processes
-
The realization of Cu-NW-based interconnects with a diameter below 25 µm under ambient conditions for fine-pitch applications
-
A detailed microstructural analysis of Cu-NW interconnects using STEM/EDX and EBSD
The shear strength data reveal significant impacts of the bonding force, the bonding temperature and the wire diameter. The strengths of Cu-NW interconnects formed at 50°C amount to approximately 5 MPa (400 nm wire diameter) and 26 MPa (100 nm) and show an increase by 20–25% in the case of additional post-bond annealing at 300°C for 1 h. The STEM and EBSD investigations of interconnects with wire diameters of 400 nm reveal indications of merged NWs. However, the broad observation of the contact areas of NWs grown from different pads remains challenging. The EDX results suggest a negligible oxidation of Cu-NWs during the bonding process at low temperatures. Cu-NW interconnects with 10 µm diameter of the Cu pad and 100 nm thin wires exhibit shear strengths around 72 MPa and up to 90.5 MPa in the case of a bonding temperature of 220°C. Table III provides an overview of Cu–Cu joints realized by TCB with conventional Cu bumps/pillars and those with nanostructured Cu bump/particles. Considering the required bonding time and the atmosphere in particular, the results of the present study demonstrates the outstanding potential of Cu-NW fine-pitch interconnects for an adoption in highly integrated heterogeneous systems. Moreover, the broad compatibility of the NW based bonding technology with both hybrid bonding and solder-based bonding and the results of previous works by NanoWired27,33,41 emphasize the potential for future mixed-pitch applications.
Addressing the broad applicability of this technology, our future research will focus on the further downscaling of Cu-NW interconnects to a pitch of 10 µm including reliability tests as well as correlations of mechanical and electrical interconnect properties in conjunction with microstructural characteristics.
References
G. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965).
T.N. Theis and H.-S.P. Wong, The end of Moore’s Law: a new beginning for information technology. Comput. Sci. Eng. 19(2), 41–50 (2017). https://doi.org/10.1109/MCSE.2017.29.
S. Zhang, Z. Li, H. Zhou, R. Li, S. Wang, K.-W. Paik, and P. He, Challenges and recent prospectives of 3D heterogeneous integration. Adv. Electr. Eng. Electr. Energy 2, 100052 (2022). https://doi.org/10.1016/j.prime.2022.100052.
P. Enquist, G. Fountain, C. Petteway, A. Hollingsworth, H. Grady, Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications. In 2009 IEEE international conference on 3D system integration, 1–6 (2009). https://doi.org/10.1109/3DIC.2009.5306533.
Y. Kagawa, N. Fujii, K. Aoyagi, Y. Kobayashi, S. Nishi, N. Todaka, S. Takeshita, J. Taura, H. Takahashi, Y. Nishimura, K. Tatani, M. Kawamura, H. Nakayama, T. Nagano, K. Ohno, H. Iwamoto, S. Kadomura, T. Hirayama, Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding. In 2016 IEEE international electron devices meeting (IEDM), 8.4.1–8.4.4 (2016). https://doi.org/10.1109/IEDM.2016.7838375.
E. Beyne, S.-W. Kim, L. Peng, N. Heylen, J. De Messemaeker, O. O. Okudur, A. Phommahaxay, T.-G. Kim, M. Stucchi, D. Velenis, A. Miller, G. Beyer, Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology. In 2017 IEEE international electron devices meeting (IEDM), 32.4.1–32.4.4 (2017). https://doi.org/10.1109/IEDM.2017.8268486.
I. Panchenko, L. Wenzel, M. Mueller, C. Rudolph, A. Hanisch, and J.M. Wolf, Microstructure development of Cu/SiO2 hybrid bond interconnects after reliability tests. IEEE Trans. Compon. Packag. Manuf. 12(3), 410–421 (2022). https://doi.org/10.1109/TCPMT.2022.3149788.
K. Suganuma, Advances in lead-free electronics soldering. Curr. Opin. Solid State Mater. Sci. 5(1), 55–64 (2001). https://doi.org/10.1016/S1359-0286(00)00036-X.
R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, P. Soussan, Cu/Sn microbumps interconnect for 3D TSV chip stacking. In 2010 proceedings 60th electronic components and technology conference (ECTC), 858–863 (2010). https://doi.org/10.1109/ECTC.2010.5490698.
I. Panchenko, J. Grafe, M. Mueller, K.-W. Wolter, Microstructure investigation of Cu/SnAg solid-liquid interdiffusion interconnects by electron backscatter diffraction, In 2013 IEEE 15th electronics packaging technology conference (EPTC 2013), 318–323. https://doi.org/10.1109/EPTC.2013.6745735.
S.-W. Lee, C.-Y. Chang, G.-M. Chang, and K.-N. Chen, Fine-feature Cu/In interconnect bonding using single sided heating and chip-to-wafer bonding technology. IEEE J. Electron Devices Soc. 5(2), 128–131 (2017). https://doi.org/10.1109/JEDS.2016.2645382.
S. Bickel, R. Hoehne, I. Panchenko, J. Meyer, I. Panchenko, M. Juergen Wolf, Cu-In Fine-pitch-interconnects with enhanced shear strength. In 2018 IEEE 68th electronic components and technology conference (ECTC), 808–813 (2018). https://doi.org/10.1109/ECTC.2018.00125.
H.Y. Yu, T.H. Yang, Y.S. Chiu, and C.R. Kao, Surface diffusion and the interfacial reaction in Cu/Sn/Ni micro-pillars. J. Electron. Mater. 49, 88–95 (2020). https://doi.org/10.1007/s11664-019-07455-5.
Y.C. Liang, C. Chen, and K.N. Tu, Side wall wetting induced void formation due to small solder volume in microbumps of Ni/SnAg/Ni upon reflow. ECS Solid State Lett. 1(4), 60–62 (2012). https://doi.org/10.1149/2.002204ssl.
K.N. Tu, Reliability challenges in 3D IC packaging technology. Microelectron. Reliab. 51(3), 517–523 (2011). https://doi.org/10.1016/j.microrel.2010.09.031.
C.C. Chang, Y.W. Lin, Y.W. Wang, and C.R. Kao, The effects of solder volume and Cu concentration on the consumption rate of Cu pad during reflow soldering. J. Alloys Compd. 429(1–2), 99–104 (2010). https://doi.org/10.1016/j.jallcom.2009.11.088.
B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabunoglu Tezcan, Z. Tokei, J. Vaes, J. Van Aelst, E. Beyne, 3D integration by Cu–Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias. In 2006 international electron devices meeting, 1–4. https://doi.org/10.1109/IEDM.2006.346786.
H. Park, H. Seo, Y. Kim, S. Park, and S.E. Kim, Low-temperature (260°C) solderless Cu–Cu bonding for fine-pitch 3-D packaging and heterogeneous integration. IEEE Trans. Compon. Packag. Manuf. Technol. 11(4), 565–572 (2021). https://doi.org/10.1109/TCPMT.2021.3065531.
C.H. Tsau, S.M. Spearing, and M.A. Schmidt, Fabrication of wafer-level thermocompression bonds. J. Microelectromech. Syst. 11(6), 641–647 (2002). https://doi.org/10.1109/JMEMS.2002.805214.
M.M.V. Taklo, P. Storås, K. Schjølberg-Henriksen, H.K. Hasting, and H. Jakobsen, Strong, high-yield and low-temperature thermocompression silicon wafer-level bonding with gold. J. Micromech. Microeng. 14, 884–890 (2004). https://doi.org/10.1088/0960-1317/14/7/007.
X. F. Ang, A. T. Lin, J. Wei, Z. Chen, C. C. Wong, Low temperature copper-copper thermocompression bonding. In 2008 10th electronics packaging technology conference, 399–404. https://doi.org/10.1109/EPTC.2008.4763467.
A. Huffman, J. Lannon, M. Lueck, C. Gregory, and D. Temple, Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration. J. Instrum. 4, P03006 (2009). https://doi.org/10.1088/1748-0221/4/03/P03006.
H. Park, and S.E. Kim, Two-step plasma treatment on copper surface for low-temperature Cu thermo-compression bonding. IEEE Trans. Compon. Packag. Manuf. Technol. 10(2), 332–338 (2020).https://doi.org/10.1109/TCPMT.2019.2928323.
N. Shahane, K. Mohan, R. Behera, A. Antoniou, P. M. Raj, V. Smet, R. Tummala, Novel high-temperature, high-power handling all-Cu interconnections through low-temperature sintering of nanocopper foams. In 2016 IEEE 66th electronic components and technology conference (ECTC), 829–836. https://doi.org/10.1109/ECTC.2016.352.
K. Mohan, N. Shahane, P. M. Raj, A. Antoniou, V. Smet, R. Tummala, Low-temperature, organics-free sintering of nanoporous copper for reliable, high-temperature and high-power die-attach interconnections. In 2017 IEEE applied power electronics conference and exposition (APEC), 3083–3090. https://doi.org/10.1109/APEC.2017.7931137
L. Du, T. Shi, Z. Tang, G. Liao, Reliable Cu–Cu thermocompression bonding by low temperature sintered Cu nanowires, In 2017 IEEE 67th electronic components and technology conference (ECTC), 1285–1290. https://doi.org/10.1109/ECTC.2017.33.
F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, D. Riehl, X. Ding, A. Kramer, K. Hofmann, Room temperature KlettWelding interconnect technology for high performance CMOS Logic. In 2021 IEEE 71st electronic components and technology conference (ECTC), 371–376. https://doi.org/10.1109/ECTC32696.2021.00069.
A. Shehzad, R. Yin, I. Panchenko, M. Mueller, S. Bickel, O. Birlem, S. Quednau, J. Wolf, Novel Cu-nanowire-based technology enabling fine pitch interconnects for 2.5D/3D Integration. In 2022 IEEE 9th electronics system-integration technology conference (ESTC), 118–123. https://doi.org/10.1109/ESTC55720.2022.9939420.
H. Jiang, S. Robertson, Z. Zhou, C. Liu, Cu–Cu Bonding with Cu Nanowire Arrays for Electronics Integration. In 2020 IEEE 8th electronics system-integration technology conference (ESTC), 1–6. https://doi.org/10.1109/ESTC48849.2020.9229670.
K. Schnabl, L. Wentlent, K. Mootoo, S. Khasawneh, A.A. Zinn, J. Beddow, E. Hauptfleisch, D. Blass, and B. Borgesen, Nanocopper based solder-free electronic assembly. J. Electron. Mater. 43, 4515–4521 (2014). https://doi.org/10.1007/s11664-014-3478-6.
X. Liu and H. Nishikawa, Low-pressure Cu–Cu bonding using in-situ surface-modified microscale Cu particles for power device packaging. Scr. Mater. 120, 80–84 (2016). https://doi.org/10.1016/j.scriptamat.2016.04.018.
Y. Yuan, H. Wu, J. Li, P. Zhu, and R. Sun, Cu–Cu joint formation by low-temperature sintering of self-reducible Cu nanoparticle paste under ambient condition. Appl. Surf. Sci. 570, 151220 (2021). https://doi.org/10.1016/j.apsusc.2021.151220.
F. Roustaie, S. Quednau, F. Weißenborn, and O. Birlem, Low-resistance room-temperature interconnection technique for bonding fine pitch bumps. J. Mater. Eng. Perform. 30, 3173–3177 (2021). https://doi.org/10.1007/s11665-021-05649-9.
I. Panchenko, L. Wenzel, S. Bickel, M. Mueller, C. Rudolph, S. Quednau, O. Birlem, A. Graff, F. Altmann, and M. Junghaenel, Hybrid bond and nanowired bump technologies for high density interconnect formation on wafer level. In 7th international conference reliability and stress-related phenomena in nanoelectronics, presentation (2023).
F. Roustaie, S. Quednau, F. Dassinger, H.F. Schlaak, M. Lotz, and S. Wilfert, In situ synthesis of metallic nanowire arrays for ionization gauge electron sources. J. Vac. Sci. Technol. B 34, 02G103 (2016). https://doi.org/10.1116/1.4939756.
C.A. Schneider, W.S. Rasband, and K.W. Eliceiri, NIH Image to ImageJ: 25 years of image analysis. Nat. Methods 9(7), 671–675 (2012). https://doi.org/10.1038/nmeth.2089.
I. Platzman, R. Brener, H. Haick, and R. Tannenbaum, Oxidation of polycrystalline copper thin films at ambient conditions. J. Phys. Chem. C 112(4), 1101–1108 (2008). https://doi.org/10.1021/jp076981k.
Y. Ma, A. Roshanghias, and A. Binder, A comparative study on direct Cu–Cu bonding methodologies for copper pillar bumped flip-chips. J. Mater. Sci.: Mater Electr. 29, 9347–9353 (2018). https://doi.org/10.1007/s10854-018-8965-8.
S. Jangam, A.A. Bajwa, U. Mogera, P. Ambhore, T. Colosimo, B. Chylak, S. Iyer, Fine-pitch (≤10 µm) direct Cu–Cu interconnects using in-situ formic acid vapor Treatment. In 2019 IEEE 69th electronic components and technology conference (ECTC), 620–627. https://doi.org/10.1109/ECTC.2019.00099.
M. Lykova, I. Panchenko, M. Schneider-Ramelow, T. Suga, F. Mu, and R. Buschbeck, Cu-Cu thermocompression bonding with a self-assembled monolayer as oxidation protection for 3D/2.5D system integration. Micromachines 14, 1365 (2023). https://doi.org/10.3390/mi14071365.
F. Roustaie, S. Quednau, F. Dassinger, O. Birlem, Room temperature interconnection technology for bonding fine pitch bumps using Nanowiring, klettwelding, klettsintering and klettglueing. In 2020 15th international microsystems, packaging, assembly and circuits technology conference (IMPACT), 168–171. https://doi.org/10.1109/IMPACT50485.2020.9268570.
Z. Wu, J. Cai, Q. Wang, and J. Wang, Low temperature Cu-Cu bonding using copper nanoparticles fabricated by high pressure PVD. AIP Adv. 7, 035306 (2017). https://doi.org/10.1063/1.4978490.
Acknowledgments
This work was supported by the Fraunhofer Society within the project “NanoInt” (Fraunhofer SME program) and by the Federal Ministry for Education and Research (BMBF) within the project “Verteilte Fertigung für neuartige und vertrauenswuerdige Elektronik – T4T” (grant no. 16ME0481). The authors gratefully acknowledge the dedication and support of the involved technical staff at NanoWired GmbH, Fraunhofer IMWS and Fraunhofer IZM-ASSID.
Funding
Open Access funding enabled and organized by Projekt DEAL.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflict of interest
The authors declare that they have no conflict of interest.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.
About this article
Cite this article
Bickel, S., Quednau, S., Birlem, O. et al. Fine-Pitch Copper Nanowire Interconnects for 2.5/3D System Integration. J. Electron. Mater. (2024). https://doi.org/10.1007/s11664-024-11107-8
Received:
Accepted:
Published:
DOI: https://doi.org/10.1007/s11664-024-11107-8