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A review of intermetallic compound growth and void formation in electrodeposited Cu–Sn Layers for microsystems packaging

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Abstract

In recent years, Cu–Sn solid–liquid interdiffusion (SLID) bonding has been used in semiconductor packaging, die-attach, fine-pitch interconnection, and through-silicon vias (TSV)-based 3D stacking applications. Due to its specific advantages such as lower cost, less stringent surface uniformity requirements, higher thermal bond stability, and relatively lower processing temperatures, electrodeposited Cu–Sn-based bonding is explored to achieve wafer-level hermetic encapsulation of miniaturized sensors; however, the overall reliability of Cu–Sn bonds remains a challenge. The voids formed in the electrodeposited Cu–Sn layers and the brittle nature of the formed intermetallic compounds (IMC) affects the long term reliability of the Cu–Sn SLID bonds. A significant concern is the sporadic interfacial void formation within the Cu–Sn layers during the bonding process and high-temperature applications. This review article summarizes the different mechanisms of the IMC formation and their growth and explores the reasons behind the interfacial voids formed in the electrodeposited Cu–Sn layers when these are annealed at different temperatures ranging from 150 to 300 °C. A detailed description of the IMC and void formation and their subsequent growth in the thick electrodeposited Cu–Sn layers is presented, along with the various design parameters affecting the IMC growth during the bonding process. Various remedies to minimize these interfacial voids are also suggested. Higher bonding pressure, lower processing temperature, and reduced surface roughness are the key factors affecting the void size and voids density. The chemical impurity in the copper electrolyte and the resultant surface roughness affect the interfacial void formation in the electrodeposited Cu–Sn layers. This review will help minimize the interfacial voids and, thus, obtain higher bond reliability.

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Funding

The authors like to acknowledge the financial support from the Industrial Research and Consulting Center (IRCC), Indian Institute of Technology (IIT) Bombay, India, under the seed grant project (RD/0515-IRCCSH0-010 (15IRCCSG002)). The authors are also thankful to the fabrication facility at the Center of Excellence in Nanoelectronics (CEN), IIT Bombay.

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  1. Electrochemical Microfabrication Laboratory, Indian Institute of Technology Bombay, Mumbai, 400076, India

    Harindra Kumar Kannojia & Pradeep Dixit

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  1. Harindra Kumar Kannojia
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HK planned and carried out the experiments and written the manuscript. PD secured the research funding, reviewed the experimental plan, analyzed the results and reviewed the manuscript.

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Correspondence to Pradeep Dixit.

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Kannojia, H.K., Dixit, P. A review of intermetallic compound growth and void formation in electrodeposited Cu–Sn Layers for microsystems packaging . J Mater Sci: Mater Electron 32, 6742–6777 (2021). https://doi.org/10.1007/s10854-021-05412-9

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