Introduction

AlGaN/GaN high-electron-mobility transistors (HEMTs) have been widely applied in switching power supplies because of their superior GaN-based properties.1,2,3,4,5,6,7,8,9,–10 These excellent properties include high electron mobility, a high breakdown field, and good thermal characteristics. At the interface of the AlGaN and GaN layers, a two-dimensional electron gas (2DEG) with a high concentration of electrons is formed as a device channel because of spontaneous and piezoelectric polarizations to further reduce on-resistance.11,12,13,14,15,16,17,18,–19 An enhancement-mode (E-mode) transistor is preferred in power switching circuits; therefore, AlGaN/GaN HEMTs with a p-GaN or p-AlGaN gate layer for depleting the underneath 2DEG channel are the major technology currently used to achieve E-mode operation.20,21,22,–23 If a p-type ohmic contact metal is used for the gate electrode, the gate will start to turn on at relatively low positive gate voltages and induce a high gate leakage current, thereby limiting the input gate voltage swing in E-mode operation. However, if a Schottky contact metal is used for the gate electrode, the gate leakage current can be reduced at a high positive gate voltage and the input gate voltage swing can be increased. When a positive gate bias is applied, diode D1 (formed by Schottky gate metal/p-GaN) is reverse-biased and D2 (formed by p-GaN/AlGaN/GaN) is forward-biased. At a high positive gate bias, the D1 formed at the gate metal and p-GaN dominate the gate leakage current because of the drop in reverse voltage on the Schottky diode. Several published studies have investigated the device characteristics of p-GaN gate AlGaN/GaN HEMTs, including their threshold voltage shift, leakage current, and degradation mechanisms.21,24,25,26,27,28,29,30,31,32,–33 However, prior research focused on the device I–V characteristics. The present study investigated the gate capacitance and device off-state characteristics of E-mode p-GaN gate HEMTs with Schottky gate metallization after gate stress for the first time. To use C–V measurement to investigate the p-GaN gate characteristics can further understand the Schottky gate diode and p-GaN/AlGaN/GaN diode after various gate bias stress. The off-state current measurement right after the gate bias stress is to reproduce the real on–off operation during the high-frequency switching. To understand the effect after positive gate bias if any effect on the off-state current and breakdown voltage.

Experimental Results and Discussion

Commercially packaged 650-V-rated devices with a gate width of 118 mm were studied. E-mode p-GaN/AlGaN/GaN HEMTs were grown on 6-in. Si substrate and fabricated by Taiwan Semiconductor Manufacturing Company. The gate length and the gate-to-drain distance are 1.4 μm and 18 μm, respectively. To investigate the p-GaN gate stability, various gate positive biases were applied for 10 s before C–V and the off-state measurements.

The gate positive biases (VGS,stress) were 1, 2, 3, 4, 5, 6, 7, 8, V with VDS = 0 V. After each VGS,stress, the gate C–V (VDS = 0 V) and off-state characteristics (VGS = 0 V) were measured and compared with the without-stress measurements. After the measurement, all voltage biases were removed for 30 min before the next stress measurement to confirm if the device could be fully recovered. Figure 1 plots the measured C–V characteristics after different gate stress voltages under frequencies of 1 kHz, 10 kHz, 100 kHz, and 1 MHz.

Fig. 1
figure 1

C–V characteristics of the E-mode p-GaN gate HEMT after different gate stress voltages. Measured at frequencies of (a) 1 kHz, (b) 10 kHz, (c) 100 kHz, and (d) 1 MHz (VDS = 0 V).

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The measured gate C–V characteristics revealed a typical off-to-on transient as the gate voltage increasing from 1 V to 3 V, indicating the threshold voltage (VTH) was approximately 2 V. Once the device was turned on, the measured capacitance remained constant. The measured capacitances in the off-state did not exhibit distinct differences; however, the capacitances measured in on-state bias conditions (for example VGS = 5 V) exhibited significant differences in the values under different gate stresses. Figure 2 shows the normalized capacitance measured at VGS = 1 V and 5 V versus various gate stresses (VG,stress) under different measurement frequencies. The normalized capacitance is the measured capacitance of each gate-stress divided by the capacitance without gate-stress. The change in the measured capacitance at VGS = 1 V was small but still demonstrated an effect from gate stress. However, a significant change was observed when the gate stress was greater than 6 V, as shown in Fig. 2b. The increase in the measured capacitance was more than 20% at low frequencies. When the device is turned on, the gate structure from the gate electrode to the 2DEG channel consists of a Schottky diode (D1) formed of gate-metal/p-GaN and a p-GaN/AlGaN/GaN diode (D2) in series, as shown in Fig. 3. As described in Ref. 23, when the VG is higher than 1.5 V, the voltage drop across D2 is almost saturated (due to the forward bias at D2) and the applied VGS is mostly across D1. Therefore, at a high positive VGS bias, the Schottky diode (D1) limits the leakage current because of reverse bias. Because the capacitance value of D1 from the depletion region is smaller than that from the forward-biased D2, the measured capacitance is the result of D1 in series with D2. Therefore, the change (increase) in Fig. 2b was attributed to the change inside D1, which was mostly in the depletion region of D1, as shown in Fig. 3c.34 Based on the two-junction model described in Ref. 34, a junction capacitor (CD1) due to the Schottky metal/p-GaN junction was added in series with the AlGaN barrier capacitor (CD2). The total capacitance value (Ctotal) is given by:

$$ \frac{1}{{C_{\text{total}} }} = \frac{1}{{C_{\text{D1}} }} + \frac{1}{{C_{\text{D2}} }}. $$
(1)
Fig. 2
figure 2

Normalized capacitance versus gate stress voltage (VGS,stress) obtained at (a) VGS = 1 V and (b) VGS = 5 V in Fig. 1 (VDS = 0 V).

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Fig. 3
figure 3

(a) Device cross section and (b) equivalent diodes (D1 and D2) and band diagram (at 0 bias), (c) band diagram (at high VGS bias) in the gate structure of an E-mode p-GaN gate HEMT.

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The CD2 is simply calculated by using the ideal dielectric constant of the AlGaN and assumed to be constant. At VGS = 5 V and VDS = 0 V, most of the applied gate voltage drops across the depletion region in the diode D1 once the 2DEG has been formed. The small-signal capacitance CD1 is given by:

$$ C_{\text{D1}} = \frac{{{\text{d}}Q_{{{\text{g}}\_{\text{pGaN}}}} }}{{{\text{d}}V_{\text{g}} }}. $$
(2)

Therefore, an increase of the measured capacitance is mostly due to the change in the charge density (Qg-pGaN) within the p-GaN layer. This was mainly because of hole/electron injection into the p-GaN region after high positive gate stress and the carriers being trapped in the p-GaN region.25 The trapped carriers resulted in a change in the measured capacitance, especially in the low-frequency measurement where the trapping/detrapping time constant was long. At measurement frequencies less than 10 kHz, the effect from high positive gate stress was significant and exhibited an increase of more than 20%. Using this characterization measurement, the quality of p-GaN can be revealed when the gate is under high positive bias.

As described previously, the measured gate C–V characteristics in Fig. 1 exhibit the typical off-to-on transient as the gate voltage increased from 1 V to 3 V. To study the shift in threshold voltage (VTH) after gate stress, the peak values of ΔC versus VGS from the C–V curves in Fig. 1 were studied, and the corresponding VGS (defined as VG,peak and VTH) in the peak values of ΔC versus various gate stress voltages (VGS,stress) was derived and plotted in Fig. 4. In this figure, the VG,peak (VTH) shift is referred to as the value change of VG,peak compared with that without gate stress (VGS,stress = 0 V). The obvious trend in Fig. 4 is a negative shift at VGS,stress of 1 V, and then a positive shift before VGS,stress increases to 6 V. Once VGS,stress is greater than 6 V, a significant negative shift is observed. A higher value of − 0.23 V was obtained after positive 8-V gate stress was applied for 10 s. This observation is similar to the results in29 for a Schottky p-GaN HEMT from a typical ID–VGS characteristic. The first positive shift was related to the electron injection, which accumulated or was trapped in the p-GaN layer. The negative shift at high gate stress bias was caused by the additional hole injection, which resulted in the negative shift observed in Fig. 4.

Fig. 4
figure 4

VG.peak shift versus the different gate stress voltages (VGS,stress = 0 is for without stress).

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The off-state characteristics were measured immediately after various gate stress voltages were applied. For example, the off-state leakage current ID was measured up to VDS of 1000 V at VGS = 0 V right after VGS,stress of 1 V for 10 s. After the off-state measurement, all voltage biases were removed for 30 min before the next stress measurement to confirm whether the device could be fully recovered. Figure 5 illustrates the measured off-state current versus the drain bias after various gate stress voltages. The packaged devices could be biased up to 1000 V without breakdown. The off-state current was as low as 10−8 mA/mm before 200 V, and then increased to 10−4 mA/mm at 1000 V. However, the off-state current increased significantly after the gate stress exceeded 6 V during the off-state characterization when the VDS was within 300 V. Figure 6 shows a plot of the off-state current versus various gate stress voltages (VGS,stress) at different VDS values. Clearly observed is the off-state current increasing significantly at VDS of 100 and 200 V after the VGS,stress exceeds 6 V. The increase is approximately three orders of magnitude. A possible reason is the negative shift of the threshold voltage while VGS,stress is larger than 6 V as shown in Fig. 4 because the off-state current was measured at VGS = 0 V. The voltage difference between the gate bias (0 V) and the VTH is reduced, thus the leakage current is possibly increased. Because of the negative shift in VTH at high gate stress bias was caused by the additional hole injection. The accumulated holes in the p-GaN slightly induce the electrons in the channel and cause the leakage current.

Fig. 5
figure 5

Off-state drain current (ID) characteristics after different gate stress voltages (VGS = 0 V).

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Fig. 6
figure 6

Off-state drain current at VDS = 100–600 V (VGS = 0 V) after different gate stress voltages.

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However, the impact of the gate stress bias was limited and the increase in the off-state current was small when the VDS was greater than 700 V.

Conclusions

This study investigated the gate capacitance and off-state current of 650-V E-mode p-GaN gate AlGaN/GaN HEMTs after various gate stress voltages. The changes in the measured capacitance in the off- and on-states demonstrated the different effects of gate stress bias. The measured off-state gate capacitance did not significantly change because no 2DEG was in the channel under the gate, and thus, the capacitance was small and changed little. However, the measured on-state capacitance significantly increased when the gate stress bias was greater than 6 V, especially at low measurement frequencies. Moreover, the on–off transient voltage shifted because of the gate stress bias. A negative shift was observed when the gate stress bias was greater than 6 V. Finally, the off-state current was measured after various levels of gate stress bias; the off-state current exhibited a significant increase after larger gate stress biases when the drain bias was low, which is related to the threshold voltage shift. In conclusion, the threshold voltage, gate capacitance, and off-state current changed significantly after gate stresses greater than 6 V for the studied p-GaN gate AlGaN/GaN HEMTs. This is why most commercial p-GaN gate HEMTs are unsuitable for biases greater than 6 V.