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A twofold bio-inspired system for mitigating SEUs in the controllers of digital system deployed on FPGA

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Abstract

Reconfigurable hardware, extensively employed in mission-critical digital applications like space and military electronics due to its adaptability, encounters the issue of soft errors, especially in control path elements, which could result in functional failure. Various system-level fault tolerance methodologies exist, and this paper implements a bio-inspired fault tolerance technique called evolvable hardware (EHW). The preferred implementation of the EHW system involves hosting the evolutionary algorithm on the processor alongside the reconfigurable hardware. However, this approach encounters delays in the intercommunication of the evolved circuit between the reconfigurable hardware and the processor. To address this issue, the paper proposes a two-tier architecture to achieve absolute fault mitigation in the controller. In this architecture, Tier-1 involves the digital implementation of the genetic algorithm on the reconfigurable hardware to mitigate errors in the controller, while Tier-2 focuses on mitigating errors occurring in Tier-1. The aim is to establish an absolute and self-resilient controller hardware to mitigate faults. The study simulates faults at the target circuit and genetic module as a proof of concept. The proposed two-tier single event upset (SEU) mitigation is deployed on Microsemi’s ProAsic3e FPGA (Field Programmable Gate Array), achieving an average efficiency of 91%. This efficiency is accompanied by ten times lesser resource utilization compared to traditional methodologies and a 30% accelerated speed when compared to hybrid evolvable systems.

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The proposed methodologies efficacy was verified with the real-time circuit. Hence, benchmarks and datasets were not utilized. Data sharing does not apply to this article as no data sets were generated or analyzed during the current study.

References

  1. Bellato M, Bernardi P, Bortolato D, Candelori A, Ceschia M, Paccagnella A, Rebaudengo M, Reorda MS, Violante M, Zambolin P (2004) Evaluating the effects of seus affecting the configuration memory of an sram-based fpga. In: Proceedings Design, Automation and Test in Europe Conference and Exhibition, vol. 1. IEEE, pp 584–589

  2. Bolchini C, Miele A, Santambrogio MD (2007) Tmr and partial dynamic reconfiguration to mitigate seu faults in fpgas. In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007). IEEE, pp 87–95

  3. Kalganova T (2000) Bidirectional incremental evolution in extrinsic evolvable hardware. In: Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware. IEEE, pp 65–74

  4. Shang Q, Chen L, Cui J, Lu Y (2020) Hardware evolution based on improved simulated annealing algorithm in cyclone v fpsocs. IEEE Access 8:64770–64782

    Article  Google Scholar 

  5. Garnica O, Glette K, Torresen J (2018) Comparing three online evolvable hardware implementations of a classification system. Genet Program Evolvable Mach 19(1):211–234

    Article  Google Scholar 

  6. Deepanjali S, Sk NM (2022) Self healing controllers to mitigate seu in the control path of fpga based system: a complete intrinsic evolutionary approach. J Electron Test 38(5):547–565. https://doi.org/10.1007/s10836-022-06027-6

    Article  Google Scholar 

  7. Ortega C, Tyrrell A (1998) Evolvable hardware for fault-tolerant applications

  8. Mange D, Sanchez E, Stauffer A, Tempesti G, Marchal P, Piguet C (1998) Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties. IEEE Trans Very Large Scale Integr (VLSI) Syst 6(3):387–399

    Article  Google Scholar 

  9. Bradley DW, Tyrrell AM (2002) Immunotronics-novel finite-state-machine architectures with built-in self-test using self-nonself differentiation. IEEE Trans Evol Comput 6(3):227–238

    Article  Google Scholar 

  10. Lie W, Feng-Yan W (2009) Dynamic partial reconfiguration in fpgas. In: 2009 Third International Symposium on Intelligent Information Technology Application, vol. 2. IEEE, pp 445–448

  11. Skorobogatov S, Woods C (2012) Breakthrough silicon scanning discovers backdoor in military chip. In: Prouff E, Schaumont P (eds) Cryptographic hardware and embedded systems—CHES 2012. Springer, Berlin, Heidelberg, pp 23–40

    Chapter  Google Scholar 

  12. Sekanina L (2003) Virtual reconfigurable circuits for real-world applications of evolvable hardware. In: International Conference on Evolvable Systems. Springer, pp 186–197

  13. Lohn J, Larchev G, DeMara R (2003) A genetic representation for evolutionary fault recovery in virtex fpgas. In: International Conference on Evolvable Systems. Springer, pp 47–56

  14. Zhu P, Yao R, Du J (2017) Design of self-repairing control circuit for brushless dc motor based on evolvable hardware. In: 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE, pp 214–220

  15. Silva GNP, Duarte RO (2018) Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. In: 2018 IEEE 19th Latin-American Test Symposium (LATS), pp 1–4. https://doi.org/10.1109/LATW.2018.8349669

  16. Wang J, Liu J (2017) Fault-tolerant strategy for real-time system based on evolvable hardware. J Circuits Syst Comput 26(07):1750111

    Article  Google Scholar 

  17. Wang J, Kang J, Hou G (2019) Real-time fault repair scheme based on improved genetic algorithm. IEEE Access 7:35805–35815. https://doi.org/10.1109/ACCESS.2019.2905042

    Article  Google Scholar 

  18. vasantha Rani SPJ, NA, R (2020) Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms. Int J Bio-inspired Comput 15:43–51

  19. Silva GNP, de Oliveira Duarte R (2018) Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. In: 2018 IEEE 19th Latin-American Test Symposium (LATS), pp 1–4

  20. Suhas S, Malhotra G, Rajini VH (2021) Hsclone genetic algorithm implementation on a combinational circuit. Iete J Res 1–9

  21. Zhang J, Cai J-y, Meng Y, Meng T (2020) A novel self-adaptive circuit design technique based on evolvable hardware. Int J Autom Comput 1–8

  22. Bradley D, Ortega-Sanchez C, Tyrrell A (2000) Embryonics+ immunotronics: a bio-inspired approach to fault tolerance. In: Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware. IEEE, pp 215–223

  23. Bradley DW, Tyrrell AM (2000) Hardware fault tolerance: an immunological solution. In: Smc 2000 Conference Proceedings. 2000 IEEE International Conference on Systems, Man and Cybernetics.’cybernetics Evolving to Systems, Humans, Organizations, and Their Complex Interactions’(cat. No. 0, vol 1. IEEE, pp 107–112

  24. Bradley DW, Tyrrell AM (2000) Immunotronics: Hardware fault tolerance inspired by the immune system. In: International Conference on Evolvable Systems. Springer, pp 11–20

  25. Khairullah SS, Elks CR (2020) Self-repairing hardware architecture for safety-critical cyber-physical-systems. IET Cyber-Phys Syst Theory Appl 5(1):92–99

    Article  Google Scholar 

  26. Khairullah SS, Elks CR (2018) A bio-inspired, self-healing, resilient architecture for digital instrumentation and control systems and embedded devices. Nucl Technol 202(2–3):141–152

    Article  Google Scholar 

  27. Morgan KS, McMurtrey DL, Pratt BH, Wirthlin MJ (2007) A comparison of tmr with alternative fault-tolerant design techniques for fpgas. IEEE Trans Nucl Sci 54(6):2065–2072. https://doi.org/10.1109/TNS.2007.910871

    Article  Google Scholar 

  28. Kumar U, Umashankar B (2007) Improved hamming code for error detection and correction. In: 2007 2nd International Symposium on Wireless Pervasive Computing. IEEE

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Funding

This work is funded by the Research Innovation Centre (RIC) of Defense Research and Development Organization (DRDO), IIT Madras Research Park, Chennai.

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Authors and Affiliations

  1. Department of CSE, Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram, Chennai, India

    S. Deepanjali & S. K. Noor Mahammad

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  1. S. Deepanjali
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  2. S. K. Noor Mahammad
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DS has designed, implemented and prepared the manuscript and the proposed methodology, and implementation with the manuscript was reviewed by NMSK.

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Correspondence to S. K. Noor Mahammad.

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Deepanjali, S., Mahammad, S.K.N. A twofold bio-inspired system for mitigating SEUs in the controllers of digital system deployed on FPGA. J Supercomput 80, 9438–9470 (2024). https://doi.org/10.1007/s11227-023-05804-0

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