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Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach

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Abstract

Single event upsets (SEU) are the transient errors that occur during the operation of the circuit. High radiation in the space environment and its invasion of the nanoelectronics can result in a bit-flip in the combinational circuits and may cause a stuck-at fault in the sequential circuit. Faults are unacceptable for any application, especially SEU in the control path, which is crucial and imperative since it can lead to functional or even mission failure. As a result, this paper proposes a bio-inspired technique based on a modified heuristic-guided genetic algorithm to mitigate error at the Finite State Machine (FSM), which is the controller’s behavior model. The proposed architecture performs an optimized functional level evolution of the FSM intrinsically on ProAsic3e FPGA boards without the help of System-on-Chip (SoC). Due to this, the delay caused by extrinsic and hybrid evolution has been reduced. The proposed heuristic-guided genetic algorithm recovers the fault in the control circuit with less convergence time when compared to the standard genetic algorithm. The resource utilization of the proposed evolvable hardware system has reduced costs compared to traditional functional evolution.

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References

  1. Álvarez I, Proenza J, Barranco M, Knezic M (2017) Towards a time redundancy mechanism for critical frames in time-sensitive networking. In: Proc. 22nd IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), pp 1–4. https://doi.org/10.1109/ETFA.2017.8247721

  2. Asselmeyer T, Ebeling W, Rosé H (1997) Evolutionary strategies of optimization. Phys Rev E 56:1171–1180. https://doi.org/10.1103/PhysRevE.56.1171

    Article  Google Scholar 

  3. Bergmann NW, Sutton PR (1998) A high-performance computing module for a low earth orbit satellite using reconfigurable logic. In: Proc. International Workshop on Field Programmable Logic and Applications, Springer, pp 416–420

  4. Bouhali M, Shamani F, Dahmane ZE, Belaidi A, Nurmi J (2017) FPGA applications in unmanned aerial vehicles-a review. In: Proc. International Symposium on Applied Reconfigurable Computing, Springer, pp 217–228

  5. Carmichael C, Fuller E, Blain P, Caffrey M (1999) SEU mitigation techniques for virtex FPGAs in space applications. In: Proceeding of the Military and Aerospace Programmable Logic Devices International Conference (MAPLD), p C2

  6. Das S, Tokunaga C, Pant S, Ma WH, Kalaiselvan S, Lai K, Bull DM, Blaauw DT (2008) Razorii: In situ error detection and correction for PVT and SER tolerance. IEEE J Solid-State Circuits 44(1):32–48

    Article  Google Scholar 

  7. El-Maleh AH, Al-Qahtani AS (2014) A finite state machine based fault tolerance technique for sequential circuits. Microelectron Reliab 54(3):654–661

    Article  Google Scholar 

  8. Garnica O, Glette K, Torresen J (2018) Comparing three online evolvable hardware implementations of a classification system. Genet Program Evolvable Mach 19(1):211–234

    Article  Google Scholar 

  9. Holland JH (1992) Genetic algorithms. Sci Am 267(1):66–73

    Article  Google Scholar 

  10. Keymeulen D, Zebulum RS, Jin Y, Stoica A (2000) Fault-tolerant evolvable hardware using field-programmable transistor arrays. IEEE Trans Reliab 49(3):305–316

    Article  Google Scholar 

  11. Koza JR, Bennett FH, Andre D, Keane MA, Dunlap F (1997) Automated synthesis of analog electrical circuits by means of genetic programming. IEEE Trans Evol Comput 1(2):109–128

    Article  Google Scholar 

  12. Kumar U, Umashankar B (2007) Improved Hamming code for error detection and correction. In: Proc/ 2nd International Symposium on Wireless Pervasive Computing, IEEE

  13. Langeheine J, Becker J, Folling S, Meier K, Schemmel J (2001) A CMOS FPGA chip for intrinsic hardware evolution of analog electronic circuits. In: Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001, IEEE, pp 172–175

  14. Lohn J, Larchev G, DeMara R (2003a) A genetic representation for evolutionary fault recovery in virtex FPGAs. In: Tyrrell AM, Haddow PC, Torresen J (eds) Evolvable Systems: From Biology to Hardware, Springer Berlin Heidelberg, Berlin, Heidelberg, pp 47–56

  15. Lohn J, Larchev G, DeMara R (2003b) A genetic representation for evolutionary fault recovery in virtex FPGAs. In: Proc. International Conference on Evolvable Systems, Springer, pp 47–56

  16. Ma X, Sun H, Xu E, Cui S, Yin B, Faied M (2020) FSM for robot target search and retrieval under semi-constructed environment. In: Proc. IEEE International Conference on Mechatronics and Automation (ICMA), pp 296–301

  17. Miller JF (1999) An empirical study of the efficiency of learning Boolean functions using a cartesian genetic programming approach. In: Proceedings of the 1st Annual Conference on Genetic and Evolutionary Computation - Volume 2, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, GECCO’99, p 1135–1142

  18. Ortega-Sánchez C, Tyrrell A (1998) Muxtree revisited: Embryonics as a reconfiguration strategy in fault-tolerant processor arrays. In: Sipper M, Mange D, Pérez-Uribe A (eds) Evolvable Systems: From Biology to Hardware. Springer, Berlin Heidelberg, Berlin, Heidelberg, pp 206–217

    Chapter  Google Scholar 

  19. Pratt B, Caffrey M, Carroll JF, Graham P, Morgan K, Wirthlin M (2008) Fine-grain SEU mitigation for FPGAs using partial TMR. IEEE Trans Nucl Sci 55(4):2274–2280

    Article  Google Scholar 

  20. Pratt B, Caffrey M, Graham P, Morgan K, Wirthlin M (2006) Improving FPGA design robustness with partial TMR. In: IEEE International Reliability Physics Symposium Proceedings, pp 226–232. https://doi.org/10.1109/RELPHY.2006.251221

  21. Rochet R, Leveugle R, Saucier G (1993) Analysis and comparison of fault tolerant FSM architecture based on SEC codes. In: Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp 9–16

  22. Ruano O, Maestro JA, Reviriego P (2009) A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs. IEEE Trans Nucl Sci 56(4):2091–2102. https://doi.org/10.1109/TNS.2009.2014563

    Article  Google Scholar 

  23. Sekanina L (2003) Virtual reconfigurable circuits for real-world applications of evolvable hardware. In: Proc. International Conference on Evolvable Systems, Springer, pp 186–197

  24. Sekanina L, Drábek V (2000) The concept of pseudo evolvable hardware. IFAC Proceedings Volumes 33(1):117–122

    Article  Google Scholar 

  25. Silva GNP, de Oliveira Duarte R (2018) Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. In: Proc. IEEE 19th Latin-American Test Symposium (LATS), pp 1–4

  26. Silva GNP, Duarte RO (2018) Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement. In: Proc. IEEE 19th Latin-American Test Symposium (LATS), pp 1–4

  27. Skorobogatov S, Woods C (2012) Breakthrough silicon scanning discovers backdoor in military chip. In: Prouff E, Schaumont P (eds) Cryptographic Hardware and Embedded Systems - CHES 2012. Springer, Berlin Heidelberg, Berlin, Heidelberg, pp 23–40

    Chapter  Google Scholar 

  28. Srivastava AK, Gupta A, Chaturvedi S, Rastogi V (2014) Design and simulation of virtual reconfigurable circuit for a fault tolerant system. In: Proc. International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014) pp 1–4

  29. Stomeo E, Kalganova T, Lambert C (2006) Generalized disjunction decomposition for the evolution of programmable logic array structures. In: Proc. First NASA/ESA Conference on Adaptive Hardware and Systems (AHS’06), IEEE, pp 179–185

  30. Suhas S, Malhotra G, Rajini VH (2021) HsClone genetic algorithm implementation on a combinational circuit. IETE J Res pp 1–9

  31. Thompson A (1995) Evolving fault tolerant systems. In: Proc. First International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications, IET, pp 524–529

  32. Thompson A, Harvey I, Husbands P (1996) Unconstrained evolution and hard consequences. In: Towards evolvable hardware, Springer, pp 136–165

  33. Thompson A, Layzell P, Zebulum RS (1999) Explorations in design space: Unconventional electronics design through artificial evolution. IEEE Trans Evol Comput 3(3):167–196

    Article  Google Scholar 

  34. Tufte G, Haddow PC (2000) Evolving an adaptive digital filter. In: Proc. Second NASA/DoD Workshop on Evolvable Hardware, IEEE, pp 143–150

    Google Scholar 

  35. Tyrrell AM, Hollingworth G, Smith SL (2001) Evolutionary strategies and intrinsic fault tolerance. In: Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001, IEEE, pp 98–106

  36. Vasantha Rani SPJ, Ranjith NA (2020) Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms. Int J Bio Inspir Com 15:43–51

  37. Wang JJ (2003) Radiation effects in FPGAs. https://doi.org/10.5170/CERN-2003-006.34

  38. Wang J, Kang J, Hou G (2019) Real-time fault repair scheme based on improved genetic algorithm. IEEE Access 7:35805–35815. https://doi.org/10.1109/ACCESS.2019.2905042

    Article  Google Scholar 

  39. Wang J, Liu J (2017) Fault-tolerant strategy for real-time system based on evolvable hardware. J Circuits Syst Comput 26(07):1750111

    Article  Google Scholar 

  40. Zhang J, yan Cai J, Meng Y, Meng T (2020) A novel self-adaptive circuit design technique based on evolvable hardware. Int J Autom Comput pp 1–8

  41. Zhang W, Li Y, He G (2007) Intrinsic evolution of frequency splitter with a new analog EHW platform. In: Proc. International Symposium on Intelligence Computation and Applications, Springer, pp 611–620

  42. Zhu P, Yao R, Du J (2017) Design of self-repairing control circuit for brushless DC motor based on evolvable hardware. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE, pp 214–220

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  1. Department of CSE, Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram, Chennai, India

    S Deepanjali & Noor Mahammad Sk

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  1. S Deepanjali
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Deepanjali, S., Sk, N.M. Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach. J Electron Test 38, 547–565 (2022). https://doi.org/10.1007/s10836-022-06027-6

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