Skip to main content
SpringerLink
Log in

Enhanced global congestion awareness (EGCA) for load balance in networks-on-chip

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

As the core count increases in a single chip, traditionally centralized communication architecture has not met the communication demand in new situations, such as system-on-chip (SoC) and chip multi-processor (CMP). Networks-on-chip (NoC), which emerges as an interconnection and communication fabric between components on a single chip, has been regarded as an effective solution. Routing algorithm plays a key role for the performance of NoCs and congestion awareness adaptive routing algorithms take more and more attentions as they have the better latency and throughput performance than the other routing algorithms. However, the existing congestion awareness adaptive routing algorithms often suffer from poor timeliness and accuracy of congestion information, which may lead to high latency and reduced throughput. To address these issues, we propose an enhanced global congestion awareness (EGCA) adaptive routing algorithm which is based on the global congestion awareness (GCA) adaptive technique. EGCA improves the distribution mechanism of congestion information of GCA, which leads to a better timeliness and accuracy of congestion information. Extensive simulations compared the proposed mechanism with typical local, region and global congestion awareness adaptive routing algorithms show that the proposed mechanism can improve system throughput by up to \(\sim \)14 and \(\sim \)8 % and reduces latency by up to \(\sim \)30 and \(\sim \)15 % compared with minimal adaptive routing and GCA, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Benini L, Micheli GD (2002) Network-on-chip: a new paradigm for systems-onchip design. In: Proceedings of the design, automation and test in Europe conference and exhibition, pp 418–419

  2. Marculescu R, Ogras UY, Peh L-S, Jerger NE, Hoskote Y (2009) Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans Comput Aided Des Integr Circuits Syst 28:3–21

    Article  Google Scholar 

  3. Pande PP, Grecu C, Jones M, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54(8):1025–1040

    Article  Google Scholar 

  4. Sankaralingam K, Nagarajan R, Gratz P, Desikan R, Gulati D, Hanson H, Kim C, Liu H, Ranganathan N, Sethumadhavan S, Sharif S, Shivakumar P, Yoder W, McDonald R, Keckler S, Burger D (2006) The distributed microarchitecture of the TRIPS prototype processor. In: International symposium on microarchitectures, pp 480–491

  5. Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Iyer P, Singh A, Jacob T, Jain S, Venkataraman S, Hoskote Y, Borkar N (2007) An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS. In: IEEE international solid state circuits conference, pp 98–99

  6. Dally WJ, Towles B (2004) Principles and practices of Interconnection Networks. Morgan Kaufmann, New York

    Google Scholar 

  7. Duato J, Yalamanchili S, Ni L (2002) Interconnection networks: an engineering approach. Morgan Kaufmann, New York

    Google Scholar 

  8. Glass CJ, Ni LM (1994) The turn model for adaptive routing. J ACM 41(5):874–902

    Article  Google Scholar 

  9. Chiu GM (2000) The odd–even turn model for adaptive routing. IEEE Trans Parallel Distrib Syst:729–738

  10. Dally WJ, Aoki H (1993) Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans Parallel Distrib Syst 4(4):466–475

    Article  Google Scholar 

  11. Kim J, Park D, Theocharides T et al (2005) A low latency router supporting adaptivity for on-chip interconnects. In: Proceedings of the 42nd annual design automation conference. ACM, pp 559–564

  12. Li M, Zeng Q-A, Jone W-B (2006) DyXY-A proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of 43rd design automation conference, pp 849–852

  13. Hu J, Marculescu R (2004) DyAD: smart routing for networks-on-chip. In: Proceedings of 41st design automation conference, pp 260–263

  14. van den Brand JW, Ciordas C, Goossens K, Basten T (2007) Congestion-controlled best-effort communication for networks-on-chip. In: Proceedings of the design, automation and test in Europe conference and exhibition, pp 1–6

  15. Gratz P, Grot B, Keckler SW (2008) Regional congestion awareness for load balance in networks-on-chip. In: High performance computer architecture, IEEE 14th international symposium on IEEE, pp 203–214

  16. Ma S, Enright Jerger N, Wang Z (2011) DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip. In: ISCA

  17. Manevich R, Cidon I, Kolodny A et al (2011) A cost effective centralized adaptive routing for networks-on-chip. In: Digital system design (DSD), 14th Euromicro conference on IEEE, pp 39–46

  18. Ramanujam RS, Lin B (2010) Destination-based adaptive routing on 2D mesh networks. In: Proceedings of the 6th ACM/IEEE symposium on architectures for networking and communications systems, p 19

  19. Ramakrishna M, Gratz PV, Sprintson A (2013) GCA: Global congestion awareness for load balance in networks-on-chip. In: Networks on chip (NoCS), 2013 seventh IEEE/ACM international symposium on, pp 1–8

  20. Dijkstra EW (1959) A note on two problems in connexion with graphs. In: Numerische mathematik, pp 269–271

  21. Palesi M, Patti D, Fazzino F (2010) Noxim: the noc simulator. http://noxim.Sourceforge.net

  22. Feng W, Shin KG (1997) Impact of selection functions on routing algorithm performance in multicomputer networks. In: Proceedings of the 11th international conference on supercomputing, pp 132–139

  23. Singh A, Dally WJ, Gupta AK, Towles B (2003) GOAL: a load-balanced adaptive routing algorithm for torus networks. ACM SIGARCH Comp Archit News 3(12):194–205

    Article  Google Scholar 

  24. Singh A, Dally WJ, Towles B, Gupta AK (2004) Globally adaptive load-balanced routing on tori. Comput Archit Lett 31(1):2

    Article  Google Scholar 

  25. Ascia G, Catania V, Palesi M, Patti D (2008) Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. Comput IEEE Trans 57(6):809–820

    Article  MathSciNet  Google Scholar 

  26. Hu W-H, Lee SE, Bagherzadeh N (2008) DMesh: a diagonally-linked mesh network-on-chip architecture. In: First international workshop on network on chip architectures workshop

  27. Kumar M, Laxmi V, Gaur MS et al (2014) CARM: congestion adaptive routing method for on chip networks[C]//VLSI design and 2014 13th international conference on embedded systems, 2014 27th international conference on IEEE, pp 240–245

  28. Gupta N, Kumar M, Laxmi V et al (2015) \(\sigma \text{ LBDR: }\) Congestion-aware logic based distributed routing for 2D NoC[C]. VLSI design and test (VDAT), 2015 19th International Symposium on IEEE, pp 1–6

  29. Zong W, Agyemen MO, Wang X et al (2015) Unbiased regional congestion aware selection function for NoCs[C]. In: Proceedings of the 9th international symposium on networks-on-chip. ACM, p 19

  30. Dana A, Salehi N (2012) Congestion aware routing algorithm for mesh network-on-chip platform. Indian J Sci Technol 5(6):2822–2830

    Google Scholar 

  31. Chang EJ, Hsin HK, Chao CH et al (2015) Regional ACO-based cascaded adaptive routing for traffic balancing in mesh-based network-on-chip systems. Comput IEEE Trans 64(3):868–875

    Article  MathSciNet  Google Scholar 

  32. Chang EJ, Hsin HK, Lin SY et al (2014) Path-congestion-aware adaptive routing with a contention prediction scheme for network-on-chip systems. Comput Aided Des Integr Circuits Syst IEEE Trans 33(1):113–126

    Article  Google Scholar 

Download references

Acknowledgments

This paper is supported by Zhejiang Provincial Natural Science Foundation of China under Grant No. LY15F020040 and No.LY16F020028, the Doctoral Scientific Research Foundation of JiaXing University under Grant No. N70514009. Humanity and Social Science Youth foundation of Ministry of Education of China under Grant no. 15YJCZH088.

Author information

Authors and Affiliations

  1. College of Mathematics Physics and Information Engineering, Jiaxing University, Jiaxing, 314000, China

    Jili Yan

Authors
  1. Jili Yan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jili Yan.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yan, J. Enhanced global congestion awareness (EGCA) for load balance in networks-on-chip. J Supercomput 72, 567–587 (2016). https://doi.org/10.1007/s11227-015-1583-9

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-015-1583-9

Keywords

Search

Navigation