1 Introduction

Owing to its capacity for either rectifying or non-rectifying behavior, the Schottky diode (SD), a fascinating electronic instrument in solid-state physics, is created when a metal junction is established for the semiconductor. The determining factor that affects whether an electrical current flows in a single direction is the height of the potential barrier created at the MS contact interface [1,2,3,4]. Nevertheless, the active dangling bonds on the semiconductor surface cannot be completely neutralized by employing traditional methods such as thermal oxidation or anodic oxide to grow an insulator layer between it and the metal [5,6,7,8,9,10]. As a result, many researchers have recently concentrated on improving these devices’ characteristics with the use of doping metal or metal-oxide into organic/polymer interlayers rather than traditional insulators because of their special features such as easy-grown procedures; known as the solid-liquid phase separation, electro-spinning, and sol–gel [11,12,13,14,15].

The efficiency of the MS structure is thought to be improved using a high-dielectric polymer or nanocomposite in terms of an increment of the potential BH at the metal/semiconductor interface and RR, a reduction in the density of surface-states (Nss) at the interface of the semiconductor and interfacial layer, and a decrease in series resistance (Rs) [16,17,18,19,20,21,22,23]. The numerous benefits of polymers, including small cost, good dielectric strength, flexibility, high capacity, adequate mechanical strength, low weight, and easy processing, lead to using them and their nanocomposites in constructing MPS structures [7, 11, 12]. The only disadvantage of pure polymers, i.e., low electric conductivity, can easily be improved by doping them with roughly 3–7% of a metal or metal oxide [13,14,15].

The thermoplastic polymer polyvinyl chloride (PVC) has excellent insulating qualities. PVC comes in stiff and soft varieties, with 1500–3000 MPa elastic moduli. It has a 100 °C melting point, however, with addition of a heat stabilizer, it can be heated to 260 °C. Due to its volume resistivity, dielectric constant values, and high-dielectric loss tangent, PVC is generally suitable for use in the production of insulating materials with low voltage and frequency [16]. PVC is a polar polymer, and some polar groups (such as C–Cl) will produce depolarization, resulting in increased dielectric constant. In addition, the chloride ions produced under degradation conditions will reduce its electrical insulation [17].

Boron nitride (BN) has become a particularly popular chemical because of its carbon-related properties. The properties of boron nitride in cubic form, which is extremely hard and thermally conductive, are like those of diamond. Boron nitride is a high heat and chemically resistant compound composed of boron and nitrogen, with the chemical formula BN. It is available in various crystalline structures that share electronic properties with carbon lattices. The hexagonal form, like graphite, is the most stable and relatively soft among boron nitride polymorphs. This type is commonly used as a lubricant and an additive in cosmetic and personal care products. Another variety, the cubic form known as c-BN with a zincblende or sphalerite structure such as diamond, is less hard than diamond but surpasses it in thermal and chemical durability [18]. The structure of BN nanotubes and carbon nanotubes (CNTs) is comparable. Like carbon nanotubes, BN nanotubes have unique physical characteristics but are not toxic. They possess various desirable qualities, including stability as an insulator, resistance to high-temperature oxidation, intriguing piezoelectricity, and optical features [19]. Beyond these attributes, BN nanotubes can be utilized to create an ideal insulating tubular shield for encapsulating certain materials. The unique properties of BN nanotubes will play a crucial role in advancing applications in the fields of electronics, optoelectronics, energy storage, nano-semiconductor technology, and biomedical science [20, 21].

Altindal et al. manufactured a MPS-type SD with a structure of Au/PVC:Sm2O3/n-Si and compared its electrical performance to an Au/n-Si (MS) diode. They discovered that the ideality factor (n) decreases from 5.85 to 2.27 and the value of ΦB0 rises from 0.59 to 0.84 eV providing that a thin film is placed at the metal/semiconductor interface. Additionally, the interface state densities and leakage current (I0) decrease in MPS-type SD compared to MS type [22].

In this study, an investigation was conducted to assess whether the interfacial layers of PVC and PVC:BN enhance the performance of the MS structure. The analysis included three semiconductor devices: Au/n-Si, Au/PVC/n-Si (referred to as MPS1), and Au/PVC:BN/n-Si (referred to as MPS2) structures. Following the synthesis of BN nanoparticles, the nanocrystalline surface structure’s average size was determined using XRD patterns and SEM. Electrical parameters, such as leakage current (I0), ideality factor (n), barrier height at zero bias voltage (ΦB0), series/shunt resistances (Rs, Rsh), rectifying rate (RR), and energy-dependent interface states density (Nss), were calculated from I–V characteristic measurements for the MS, MPS1, and MPS2 structures. Finally, the current conduction mechanism in these structures was examined under reverse and forward bias voltages.

2 Experimental details

2.1 Synthesis of BN nanoparticles and preparation of PVC:BN nanocomposite

To synthesize BN nano-powder, the precursors of Boric acid (H3BO3), and hydrazine monohydrate (N2H4H2O) were employed. Initially, deionized water was used to dissolve 2.5 g of H3BO3 and 8 g of NaN3 with the magnetic stirring process for 30 min. The mixture was then incubated at a temperature of 300 °C for 16 h in a nitrogen-filled muffle furnace. After the incubation period was over, the mixture was rinsed with deionized water before being vacuumed for 2–3 h at a temperature of 100 °C in a vacuum pump. It is necessary to mention that the PVC:BN nanocomposite was resulted by dissolving 0.5 g of the PVC polymer powder into 99.5 ml of deionized water and then evenly dispersing 10 mg of BN nano-powder into 5 ml of the resulting solution.

2.2 The manufacturing procedure the MS and MPS structures

A one-side polished n-Si wafer with a diameter of 5.08 cm, a thickness of 300 μm, a resistivity of 1–10 Ω.cm, and a float-zone of (100) was used for the fabrication of the MS-, MPS1-, and MPS2-type SDs. Before manufacture, n-Si wafers were first washed with deionized water for about 10 min in an ultrasonic bath after being submerged in ammonium peroxide to eliminate the native oxide layer formed at two sides of the wafer. Next, it was rinsed for 3 min in a solution/mixture of acetone, ammonium hydroxide, hydrogen peroxide, hydrofluoric acid, and deionized water. After rinsing with deionized water for 10 min, the n-Si wafer was thoroughly dried using pure nitrogen gas (N2). Subsequently, a layer of high-purity (99.99%) Au, with a thickness of 150 nm, was thermally evaporated onto the entire back side of the cleaned n-Si wafer in a high-vacuum metal-evaporation system at a pressure of 10−6 Torr. The wafer was then annealed in an atmosphere of N2 gas at a temperature of 550 °C for five minutes to establish a reliable back-ohmic contact.

Circular-shaped Au rectifier contacts, with an area of 7.85 × 10−3 cm2 and a thickness of 150 nm, were applied to a section of the n-Si wafer, which was divided into three portions to create the Au/n-Si (MS) structure (refer to Fig. 1). To produce Au/PVC/n-Si and Au/PVC:BN/n-Si MPS-type semiconductor devices (SDs) under identical conditions, similarly shaped Al rectifier contacts were thermally deposited onto the PVC polymer and PVC:BN nanocomposite layers. Thus, the fabrication process for three distinct SDs (MS, MPS1, and MPS2) was completed. Figure 2 illustrates the schematic of the constructed MPS-type SD and its corresponding energy-band diagram. It is worth noting that a KEITHLEY (Model 2450) device was utilized to measure the forward-reverse I–V characteristics of each prepared sample at room temperature.

Fig. 1
figure 1

a The schematic of the fabricated MS structure and b corresponding energy-band diagram

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Fig. 2
figure 2

a The schematic representation of the fabricated MPS structure and b corresponding energy-band diagram

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2.3 XRD analysis of BN nanostructure

The BN nanostructure was characterized using the Philips X-pert instrument with Cu kα radiation at the wavelength of 1.55 Å. Figure 3 depicts the XRD pattern of the synthesized BN nanostructure that has a largest peak at 2θ = 26.3° related to the Muller index of 200. As seen, other peaks at 2θ = 41.3°, 43.4°, 54.6°, and 75.6° related to Muller indices of 100, 101, 004, and 110 are supported by # JCPDF card No. 73-2095 [24]. The BN nanostructures are in hexagonal phase with a = 2.503 Å and c = 6.661 Å. Additionally, the Scherrer formula can be used to determine the crystallite sizes of the BN nanostructures [25]:

$$D=\frac{0.9\lambda }{\beta cos\theta }$$
(1)

where θ refers to the Bragg angle, β denotes the FWHM of the highest peak in the XRD pattern, λ and D being the X-rays wavelength and the crystalline size, respectively. The crystalline size of the BN nanoparticles is computed as 35 nm.

Fig. 3
figure 3

XRD pattern of BN nanostructure

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2.4 SEM

The SEM picture of the BN nanostructure is taken by the SEM (model LEO 1430 VP) to study the surface morphology of the prepared BN nanostructures. Figure 4 represents the SEM images of the synthesized BN nanostructure. It is obvious that the polydispersity and agglomerated BN nanoparticles, whose mean size is less than 1 μm, have been produced with various configurations.

Fig. 4
figure 4

SEM images of the BN nanoparticles

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3 Results and discussion

In the MS- and MPS-type SDs, the transit of highly energetic electrons from the top of the potential barrier can be examined using TE theory. Given that n > 1 and Rs are present in MS or MPS type SDs, the relationship between forward voltage and current for V ≥ 3kT/q is defined as follows [26, 27]:

$$ I = I_{0} \left[ {exp\left( {\frac{{q(V - IR_{s} }}{{nkT}}} \right) - 1} \right] $$
(2)

where IRs, n, and I0 represent the voltage drop across the diode’s series resistance, ideality factor, and leakage current, respectively. The semi-logarithmic representations of the I–V characteristics profiles for the MS and MPS-type semiconductor devices at forward and reverse bias voltages are illustrated in Fig. 5a. Additionally, the value of I0 is determined by utilizing the linear segment of the ln(I)-V curve at the forward bias voltage, as shown in Fig. 5b [26]. :

$$ I_{0} = AA^{*} {\text{exp}}\left( { - \frac{{q\Phi _{{B0}} }}{{kT}}} \right) $$
(3)

with ΦB0 being the barrier height at V = 0, A* is the impressive Richardson constant, and A is the area of the Schottky or rectifier constant. The amount of I0 for MS-, MPS1-, and MPS2-type SD is 2.04 × 10−5 A, 1.12 × 10−6 A, and 2.05 × 10−6 A, respectively. If compared to the MS structure, the reverse-saturation current of the MSP1- and MPS2-type SDs is one order smaller. Using Eq. (3), the ΦB0 quantity is given by [28]:

$${{\Phi }}_{B0}=\frac{kT}{q}\text{l}\text{n}\left(\frac{A{A}^{*}{T}^{2}}{{I}_{0}}\right)$$
(4)

The determined values of ΦB0 for the MS, MPS1, and MPS2 semiconductor devices are 0.559 eV, 0.635 eV, and 0.619 eV, respectively. Following this, the ideality factor of the manufactured structures can be derived by utilizing the slope of the linear section of the ln(I)-V curve [29]:

$$n=\frac{q}{kT}\left(\frac{dV}{d\left(lnI\right)}\right)$$
(5)

The computed values of n are 7.73 for MS, 6.88 for MPS1, and 7.03 for MPS2 structures. The doped polymer interlayer with high-dielectric value causes the n to diminish when the interfacial polymer layer is applied. It is necessary to note that the presence of thin films among the metal and semiconductor interface, width of the depletion layer, the inhomogeneity of the formed barrier at the interface of metal and semiconductor layers, and Nss often have an impact on the ideality factor value. Moreover, several other processes including generation-recombination at 25 °C or higher, image-force reduction, and tunneling at the Schottky barrier by surface states or traps can influence the quantity of n as well as current conduction/transport mechanisms (CCMs/CTMs) [29, 30].

It is seen from Fig. 5a that these structures’ rectifying behavior is good, particularly for MPS-type SDs. At the voltages of ± 3 V, the values of the rectifying ratio, defined as RR = IF/IR, are 11.1 for the MS, 38.4 for MPS1, and 81.9 for MPS2 structures. Comparing these values reveals that MPS-type SDs have a larger RR value than MS-type SD because PVC and the PVC:BN polymer interfacial layers have a passivated influence on Nss and lowers Rs. Because of the BN nanoparticles in the PVC polymer layer, the MPS2-type SD possesses a higher RR value. Doping BN nanostructures into the PVC polymer layer, which is placed at metal/semiconductor interface, hence causes a reduction in I0 and n as well as an increase in BH and RR values.

Fig. 5
figure 5

a The semi-logarithmic curves of I–V characteristic, and b Ln(I)–V graphs for the prepared samples.

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Additionally, the efficiency of MS- and MPS-type SDs is influenced by the series (Rs) and shunt (Rsh) resistances, two critical parameters [1, 23, 31, 32]. The quantity of Rsh is just acquired by the Ohm’s law (\({R}_{i}=d{V}_{i}/d{I}_{i}\)) from the I–V measurement at sufficient low reverse bias voltage but the Rs quantity could be computed using the TE, Norde, Cheung, and Nicollian-Brews procedures from the I–V data at the forward bias voltage and the C and G measurement at the accumulation region [1].

The profiles of Ri depending on the applied bias voltages for the MS-, MPS1-, MPS2-type SDs are semi-logarithmically demonstrated in Fig. 6. The real parts of Ri quantity, corresponded to the series (Rs) and shunt (Rsh) resistances, are practically fixed at the forward and reverse voltage biases (± 3 V), as shown in Fig. 6. Therefore, the obtained values of Rs for the MS-, MPS1-, MPS2-type SDs are 550 Ω, 825 Ω, and 556 Ω at the voltage of + 3 V, respectively. In addition, the quantities of Rsh at the bias voltage of -3 V are determined as 6.08 kΩ for MS, 31.6 kΩ for MPS1, and 45.5 kΩ for MPS2 structures. It is clear from comparing these numbers that the existence of the PVC:BN nanocomposite layer between the metal and semiconductor layers of the MPS2-type SD results in improving the rectifying ratio by reducing leakage current, series resistance, and raising shunt resistance.

Fig. 6
figure 6

The R i curves vs. V for the prepared samples

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The following two relationships, named Cheung functions, are used to calculate the main electronic parameters (ΦB0, Rs, and n) at the region of sufficiently strong forward bias voltage, which corresponds to the concave-curvature of Ln(I)-V profiles [33];

$$\frac{dV}{d\left(lnI\right)}=I{R}_{s}+\left(\frac{nkT}{q}\right)$$
(6a)
$$H\left(I\right)=V-\frac{nkT}{q}\text{ln}\left(\frac{I}{{A}^{*}A{T}^{2}}\right)=I{R}_{s}+n{{\Phi }}_{B0}$$
(6b)

The presence of native or deposited interfacial layers and series resistance typically leads to deviations from linearity in ln(I)-V graphs, particularly in the forward bias region. Cheung functions display a linear segment in this range of applied voltages, enabling the derivation of (Rs, n) and (Rs, ΦB0) parameters by utilizing the slope and intercept of dV/d(lnI)-I and H(I)-I graphs, respectively [33]. .

Figure 7 illustrates the I-dependent dV/d(lnI) and H(I) profiles for three different SDs. As can be seen, the extensive current range exhibits a well-linear behavior, making it possible to calculate the values of n, Rs, and ΦB0 using their slopes and intercepts. The key electrical parameters (n, Rs, and ΦB0) computed by the TE theory and Cheung approaches are presented in Table 1 for manufactured SDs.

Fig. 7
figure 7

Variations of dV/dln(I) and H(I) vs. I graphs of the manufactured SDs

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Generally, when the ln(I)-V graph deviates from linearity behavior, the Norde function is also able to provide the quantities of ΦB0 and Rs for the MS- and MPS-type SDs as follows [32]:

$$F\left(V\right)=\frac{V}{\gamma }-\frac{kT}{q}\text{l}\text{n}\left(\frac{I}{{A}^{*}A{T}^{2}}\right)$$
(7)

with γ being an integer number greater than ideality factor. Figure 8 represents the voltage-dependent F(V) for the fabricated based on Eq. (7). The values of ΦB0 and Rs could be obtained with utilization of a minimum point found at the concave part of the F(V) function as [32]:

$${{\Phi }}_{B0}=F\left({V}_{min}\right)+\frac{{V}_{min}}{\gamma }-\frac{kT}{q}$$
(8a)
$${R}_{s}=\frac{kT}{q}\frac{(\gamma -n)}{{I}_{min}}$$
(8b)
Fig. 8
figure 8

The voltage-dependent F(V) function for the fabricated samples

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Here, the minim point of F(V) function gives the parameters of Vmin and Imin. Table 1 introduces the ΦB0 and Rs values given by the Norde function.

It must be noted that the interface states (Nss) and non-uniformly doped atoms are to blame for a diode’s less-than-ideal behavior. The voltage-dependent Nss profile in the equilibrium condition is defined as [1, 34]:

$$ N_{{ss}} \left( V \right) = \frac{1}{q}\left[ {\frac{{\varepsilon _{i} }}{\delta }\left( {n\left( V \right) - 1} \right) - \frac{{\varepsilon _{s} }}{{W_{D} }}} \right] $$
(9)

where WD denotes the depletion layer width, δ refers to the interlayer thickness, εs and εi being the permittivity of semiconductor and interfacial layer. The energy distinction between the conduction band edge and the Nss level at a n-type semiconductor is defined as follows [1,2,3, 34]:

$${E}_{c}-{E}_{ss}=q({{\Phi }}_{e}-V)$$
(10)

In addition, the formula of n(V) and Rs gives the effective barrier height (Φe) as:

$$ \Phi _{e} - \Phi _{{B0}} = \left( {1 - \frac{1}{{n\left( V \right)}}} \right)(V - IR_{s} ) $$
(11)

Based on the Eqs. (9, 10 and 11), the energy-dependent Nss plots for the manufactured structures are presented in Fig. 9. The peak of the Nss curve for the MS-type SD is 6.74 × 1013 eV−1.cm−2, but the Nss values for the MPS1- and MPS2-type SDs are 1.78 × 1013 eV−1.cm−2 and 1.79 × 1013 eV−1.cm−2, respectively. Thus, inserting PVC and PVC:BN interfacial layers reduce the maximum of the Nss value for MS-type SD because they passivate the semiconductor surface [35,36,37].

Fig. 9
figure 9

Change of the energy dependent N ss curves for the prepared samples

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Table 1 shows the primary electric parameters and Nss density of the MS- and MPS-type SDs as determined by utilizing the Ohm’s law, TE theory, Cheung, and Norde functions. As observed, using PVC and PVC:BN interfacial layers at the interface of the metal and semiconductor layers reduces the value of n in MPS-type SDs. Based on [n = 1 + di/εs(εs /Wd+qNss)], the value of n, which represents the quality prepared SD, may deviate significantly from unity in practice due to a number of factors, including the presence of an interlayer, its thickness (di) and dielectric constant (εi), the measure of donor or acceptor atomic dopants, depletion layer width (Wd), a specific distribution of Nss at the interface between the semiconductor and the interlayer, energy states in the semiconductor’s band gap, image-force lowering of the semiconductor, generation-recombination electric charges, tunnelling through surface/interface-states, and barrier non-uniformities at the M/S interface [1,2,3,4,5,6]. On the other hand, the presence of these interlayers causes the BH of the MPS-type SDs to increase. It must be noted that the impurity bands introduced by lattice mismatches (broken bonds) between different layers are ignored, resulting in ΦB0 being underestimated [38]. Moreover, the trap or recombination central action introduced by doping is ignored, resulting in an overestimation of the effective current [39]. By increasing the Rsh and ΦB0 as well as decreasing the I0, Rs, n, and Nss, these interlayers improve the efficiency of the MS structure and the rectifying ratio. Regarding the values shown in Table 1, the results of the various calculations methods are in strong agreement with one another. These findings demonstrate that the PVC:BN interfacial layer, which has higher BH, Rsh, and RR and smaller I0, Rs, n, and Nss, can enhance the efficiency of the MS-type SD greater than traditional SiO2. Similar results for the employed high-dielectric interfacial layer were also reported in the literature [7, 9, 29].

Table 1 Electric factors of the prepared SDs determined using various approaches
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The free carrier current can also be affected by the interfacial layer, both in the reverse and forward bias voltage. Figure 10 shows the graphs of ln(IF)-VF for the MS- and MPS-type SDs fabricated in this research, which have two regions for the MS-type SD and three regions each for the MPS1- and MPS2-type SDs, each representing a separate conduction mechanism (CCM). Generally, deep trap creation at the interface of the interlayer and semiconductor can improve charge transmission. The slope of the two and three linear sections of the ln(IF)-VF profiles for the MS-type SD is equal to 1.0.9, 1.65; for the MPS1-type SD, it is 1.03, 3.20, 1.59; and for the MPS2-type SD, it is 1.48, 3.05, 2.01. When the slope’s value is close to one, the semiconductor exhibits an ohmic manner (I–V) with the low voltage bias observed at section I, meaning the electrodes inject small charges into the semiconductor [1, 22, 34]. As a result of the predominance of the recombination-tunneling process, the current at section II reveals an exponential behavior of I–exp(V) by a slope greater than two [37]. Furthermore, the trap distribution of the space-charge limited current (SCLC) at the BN nanostructures band gap causes the current to alter similar to a power function (I–V2) at section III of the MSP1- and MPS2-type SDs. It should be emphasized that the SCLC transport process only manifests when the charge content under equilibrium conditions is sufficiently lower than the charge concentration that was injected. Additionally, the increase in the number of electrons injected from the electrode causes the traps to fill up and the space charge to rise in the SCLC mechanism [1, 27, 34].

Fig. 10
figure 10

The ln(I F )-V F profiles for the a MS, b MPS1, and c MPS2 structures

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To examine the CCMs into MS- and MPS-type SDs at the reverse voltage bias, the change of the ln(IR)-VR0.5 curves are introduced in Fig. 11. At the reversed-voltage bias, the mechanism of Poole-Frenkel (PF) and Schottky emissions might occur. Once PFE type CCM is overcome, the reverse electric current (IR) is given by [29, 34, 37]:

$${I}_{R}={I}_{0}\text{e}\text{x}\text{p}\left(\frac{{\beta }_{PF}}{kT}\sqrt{\frac{V}{d}}\right)$$
(12)

But it is indicated by the following relationship providing that the SE type CCM is predominance,

$${I}_{R}=A{A}^{*}{T}^{2}\text{e}\text{x}\text{p}(-\frac{{{\Phi }}_{B}}{kT})\text{e}\text{x}\text{p}\left(\frac{{\beta }_{SC}}{kT}\sqrt{\frac{V}{d}}\right)$$
(13)

where βPF and βSC stand for the respective field lowering coefficients for the PFE and SE processes. The βPF-βSC relationship is typically expressed as follows [1, 29, 30]:

$$ 2\beta _{{SC}} = \beta _{{PF}} = \left( {\frac{{q^{3} }}{{\pi \varepsilon _{0} \varepsilon _{r} }}} \right)^{{1/2}} $$
(14)

with \({\epsilon }_{r}\) being the interlayer permittivity. Figure 11 illustrates linear behavior of the plots with a slope equal to the field lowering coefficient. According to the calculations, these numbers are 2.11 × 10−6 eV−1 m0.5V0.5 for MS-type SD, 1.81 × 10−5 eV−1 m0.5V0.5 for MPS1-type SD, and 1.00 × 10−5 eV−1 m0.5V0.5 for MPS2-type SD. For the MS-, MPS1-, and MPS2- SDs, the theoretical findings of PF are equivalent to 4.85 × 10−5 eV−1 m0.5V0.5, 1.34 × 10−5 eV−1 m0.5V0.5, and 1.39 × 10−5 eV−1 m0.5V0.5. It may be determined by comparing theoretical findings and experimental results that the SE mechanism dominates for MS-type SD at reverse bias region whereas the PFE mechanism is prevailing for MPS-type SDs.

Fig. 11
figure 11

The plot of ln(I R )-V R 0.5 for the MS-, MPS1-, and MPS2-type SDs

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4 Conclusions

In this research, three MS-, MPS1-, and MPS2-type SDs with structures of Au/n-Si, Au/PVC/n-Si, and Au/PVC:BN/n-Si were carried out on the same n-Si wafer under the similar conditions. The key electronic features of these manufactured structures, namely I0, BH, n, Rs, Rsh, RR, and Nss, were derived using the various approaches and compared to one another with the measurement of I–V characteristics at the reverse and forward bias regions. In addition, the voltage-dependent ΦB0 and n into considered determine the energy-dependent Nss density for three prepared samples. The computed I0, ΦB0, and n quantities were equal 2.04 × 10−5 A, 0.56 eV, 7.73 for MS-type SD, 1.12 × 10−6 A, 0.63 eV, 6.89 for MPS1-type SD, and 2.05 × 10−6 A, 0.62 eV, 7.03 for MPS2-type SD. It was discovered that the MPS2-type SD’s RR was 7 times more than the MS-type SD’s. Additionally, estimates of the MS, MPS1, and MPS2 structures’ CCM were made at the reverse and forward bias region. The ln(IR)-VR0.5 graphs in the reverse voltage bias demonstrate that the PFE process occurs in the MPS structures while the SE-type CCM dominates in the MS structure. These experimental findings indicate that the PVC:BN interfacial layer enhances the efficiency of the MS structure by increasing ΦB0, Rsh, and RR and decreasing n, Rs, and Nss. Due to low cost, flexibility, small weight per molecule, and simple and inexpensive production processes, PVC:BN interfacial layer is therefore possible to successfully replace an interfacial insulator layer created by standard methods.