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Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip

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Abstract

This article examines the signal integrity problem arising due to resistive drop, inductive noise and electro- migration, causing voltage fluctuations known as supply noise in an integrated circuit. Insertion of decoupling capacitor is a commonly used technique for reducing the supply noise. In this article symbiotic organism search (SOS) algorithm is used to estimate the decap. Another relevant issue addressed is the distribution of the decap over the chip. To get the best possible results in the post-layout stage pruning technique is used for partitioning and particle swarm optimization (PSO) algorithm is applied in the floorplanning stage. The purpose of this work is to reduce the supply noise without much affecting other design parameters of the chip. Simulation results show that supply noise has been reduced by up to 74.07% and the decap budget has been reduced by up to 37.4%. This approach can be used for any system-on-chip.

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Acknowledgment

This work was supported by I.I.T. Kharagpur.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Maulana Abul Kalam Azad University of Technology, Haringhata, 741249, India

    Partha Mitra

  2. Department of Electronics And Telecommunication Engineering, Jadavpur University, Kolkata, 700032, India

    Jaydeb Bhaumik

  3. Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani, 741235, India

    Angsuman Sarkar

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  1. Partha Mitra
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  2. Jaydeb Bhaumik
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Correspondence to Partha Mitra.

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Responsible Editor: V. D. Agrawal.

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Mitra, P., Bhaumik, J. & Sarkar, A. Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip. J Electron Test 37, 151–155 (2021). https://doi.org/10.1007/s10836-021-05931-7

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  • DOI: https://doi.org/10.1007/s10836-021-05931-7

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