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Efficient Placement of Distributed On-Chip Decoupling Capacitors

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On-Chip Power Delivery and Management

Abstract

Decoupling capacitors are widely used to manage power supply noise [281] and are an effective way to reduce the impedance of power delivery systems operating at high frequencies [28, 29]. A decoupling capacitor acts as a local reservoir of charge, which is released when the power supply voltage at a particular current load drops below some tolerable level. Since the inductance scales slowly [129], the location of the decoupling capacitors significantly affects the design of the power/ground networks in high performance integrated circuits such as microprocessors. At higher frequencies, a distributed system of decoupling capacitors are placed on-chip to effectively manage the power supply noise [279].

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References

  1. M. Popovich, E.G. Friedman, Decoupling capacitors for multi-voltage power distribution systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(3), 217–228 (2006)

    Google Scholar 

  2. M. Popovich, E.G. Friedman, Impedance Characteristics of Decoupling Capacitors in Multi-Power Distribution Systems, in Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 160–163, Dec 2004

    Google Scholar 

  3. A.V. Mezhiba, E.G. Friedman, Inductive properties of high-performance power distribution grids. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 10(6), 762–776 (2002)

    Google Scholar 

  4. A.V. Mezhiba, E.G. Friedman, Scaling trends of on-chip power distribution noise. IEEE Trans. Very Large Scale Integr. (VLSI) Circuits 12(4), 386–394 (2004)

    Google Scholar 

  5. L.D. Smith, R.E. Anderson, D.W. Forehand, T.J. Pelc, T. Roy, Power distribution system design methodology and capacitor selection for modern CMOS technology. IEEE Trans. Adv. Packag. 22(3), 284–291 (1999)

    Article  Google Scholar 

  6. J. Kim, B. Choi, H. Kim, W. Ryu, Y. Yun, S. Ham, S.-H. Kim, Y. Lee, J. Kim, Separated role of on-chip and on-PCB decoupling capacitors for reduction of radiated emission on printed circuit board, in Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, pp. 531–536, Aug 2001

    Google Scholar 

  7. S.B. Chen, C.H. Lai, A. Chin, J.C. Hsieh, J. Liu, High-density MIM capacitors using Al2O3 and AlTiO x dielectrics. IEEE Electron Device Lett. 23(4), 185–187 (2002)

    Article  Google Scholar 

  8. H. Hu et al., High performance ALD HfO2–Al2O3 laminate MIM capacitors for RF and mixed signal IC applications, in Proceedings of the IEEE International Electron Devices Meeting, pp. 15.6.1–15.6.4, Dec 2003

    Google Scholar 

  9. Applications of Metal-Insulator-Metal (MIM) Capacitors, International SEMATECH, Technology Transfer No. 00083985A-ENG, Oct 2000.

    Google Scholar 

  10. M. Popovich, E.G. Friedman, M. Sotman, A. Kolodny, R.M. Secareanu, Maximum effective distance of on-chip decoupling capacitors in power distribution grids, in Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration, pp. 173–179, Mar 2006

    Google Scholar 

  11. M. Popovich, E.G. Friedman, Noise aware decoupling capacitors for multi-voltage power distribution systems, in Proceedings of the ACM/IEEE International Symposium on Quality Electronic Design, pp. 334–339, Mar 2005

    Google Scholar 

  12. H.H. Chen, S.E. Schuster, On-chip decoupling capacitor optimization for high-performance vlsi design, in Proceedings of the IEEE International Symposium on VLSI Technology, Systems, and Applications, pp. 99–103, May 1995

    Google Scholar 

  13. H. Su, S.S. Sapatnekar, S.R. Nassif, Optimal decoupling capacitor sizing and placement for standard cell layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4), 428–436 (2003)

    Article  Google Scholar 

  14. S. Zhao, K. Roy, C.-K. Koh, Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), 81–92 (2002)

    Article  Google Scholar 

  15. M.E. Van Valkenburg, Network Analysis (Prentice Hall, Upper Saddle River, 1974)

    MATH  Google Scholar 

  16. M. Takamiya, M. Mizuno, A 6.7 fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL. IEEE J. Solid-State Circuits 40(3), 719–725 (2005)

    Google Scholar 

  17. V. Kursun, E.G. Friedman, Multi-Voltage CMOS Circuit Design (Wiley, Hoboken, 2006)

    Book  Google Scholar 

  18. M. Anis, Y. Massoud, Power design challenges in deep-submicron technology, in Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, pp. 1510–1513, Dec 2003

    Google Scholar 

  19. D. Deleganes, J. Douglas, B. Kommandur, M. Patyra, Designing a 3 GHz, 130 nm, Intel Pentium 4 Processor, in Proceedings of the IEEE Symposium on VLSI Circuits, pp. 130–133, June 2002

    Google Scholar 

  20. R. McGowen, C.A. Poirier, C. Bostak, J. Ignowski, M. Millican, W.H. Parks, S. Naffziger, Power and temperature control on a 90-nm itanium family processor. IEEE J. Solid-State Circuits 41(1), 229–237, Jan 2006

    Google Scholar 

  21. S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, M. Horowitz, The implementation of a 2-Core, multi-threaded itanium family processor. IEEE J. Solid-State Circuits 41(1), 197–209 (2006)

    Article  Google Scholar 

  22. T. Hubing, Effective strategies for choosing and locating printed circuit board decoupling capacitors, in Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, pp. 632–637, Aug 2005

    Google Scholar 

  23. Mathematica 5.2, Wolfram Research, Inc.

    Google Scholar 

  24. M.P. Goetz, Time and frequency domain analysis of integral decoupling capacitors. IEEE Trans. Compon. Packag. Manuf. Technol. Pt. B: Adv. Packag. 19(3), 518–522 (1996)

    Article  Google Scholar 

  25. T. Murayama, K. Ogawa, H. Yamaguchi, Estimation of peak current trough CMOS VLSI circuit supply lines, in Proceedings of the ACM Asia and South Pacific Design Automation Conference, pp. 295–298, Jan 1999

    Google Scholar 

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P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). Efficient Placement of Distributed On-Chip Decoupling Capacitors. In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_13

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  • DOI: https://doi.org/10.1007/978-3-319-29395-0_13

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