Abstract
In this paper, a new analytical approach is presented to study the effect of commonly used topologies on the energy consumption and delay of on chip network (NOC) testing using IEEE 1149.1 standard. Here, first we model the energy of each module in JTAG standard, and then using test access port (TAP) controller state diagram and test algorithm, the totoal energy based on each topology is calculated. In addition, the number of clocks is calculated and together with the propagation delay of basic gates, the test time is modelled and calculated. Using the results we can choose the least energy-consuming and fastet topology in terms of testing. The modelling is verified using FPGA implementation.
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1149.1-1990 - IEEE standard test access port and boundary-scan architecture
Aerts J, Marinissen EJ (1998) Scan chain design for test time reduction in core-based ICs, Proceedings of the International Test Conference, p 448–457
Ahmed N, Tehranipour M, Nourani M (2003) Extending JTAG for Testing Signal Integrity in SoCs, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’03)
Banerjee A, Mullins R, Moore S (2007) A power and energy exploration of network-on-chip architectures, Proc. First Int Symp Net Chip, p 163–172
Banerjee N, Vellanki P, Chatha K (2004) A power and performance model for network-onchip architectures, Proc. Design Automat est in Eur Conf Exhibit, p 1250–1255
Cota E, Carro L, Wagner F, Lubaszewski M (2003) Power-aware NOC reuse on the testing of core-based systems, Proc. International Test Conference, p 612–621
Feng Y, Lin H, Qiang X (2008) Re-Examining the Use of Network-on-Chip as Test Access Mechanism, Proc. Design, Automation and Test in Europe Conference and Exhibition, p 808–811
Ghadiry MH, Nadi M, Manzuri-Shalmani MT, Rahmati D (2007) Effect of number of faults on noc power and performance, Proc. International Conference on Parallel and Distributed Systems, p 1–9
Ghadiry M, Nadi M, Rahmati D (2008) New approach to calculate energy on NOC, Computer and Communication Engineering, p 1098–1104
Goel SK, Marinissen EJ (2002) Effective and efficient test architecture design for SOCs, Proc. International Test Conference, p 529–538
Grecu C, Ivanov A, Saleh R, Sogomonyan E, Pande P (2006) On-line fault detection and location for noc interconnects, Proc. 12th IEEE International On-Line Testing Symposium
Kahng A, Li B, Peh LS, Samadi K (2012) “A power-area simulator for interconnection networks”. IEEE Trans Very Large Scale Integr VLSI Syst 20:191–196
Meloni P, Loi I, Angiolini F et al (2006) Area and power modeling for networks-on-chip with layout awareness. VLSI Des 2007:50285–12
Murali S, Theocharides T, Vijaykrishnan N, Irwin M, Benini L, Micheli GD (2005) Analysis of error recovery schemes for networks on chips, Design & Test of Computers, p 434–442
Nadi M, Ghadiry M, Ooi CY, Marsono MN (2013) A semi-analytical approach to study the energy consumption of on-chip networks testing. J Low Power Electron 9:189–197
Nadi Senejani M, Ghadiry M, Ooi CY, Marsono MN (2015) Built-in self test power and test time analysis in on-chip networks. Circuits Syst Signal Process 34:1057–1075
Nourmandi-Pour R, Khadem-Zadeh A, Masoud Rahmani A (2010) An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip. Microelectron J 41:417–429
Pande P, Ganguly A, Feero B, Belzer B, Grecu C (2006) Design of low power reliable networks on chip through joint crosstalk avoidance and forward error correction coding, Proc. Defect and Fault Tolerance in VLSI Systems, p 466–476
Patel C, Yalamanchili SCS, Schimmel D (1997) Power constrained design of multiprocessor interconnection networks, Proc. Int Conf Comput Des, pp. 408–416
Rajagopal RS, Nadi M, Ooi CY, Marsono MN (2011) Multi-TAP architecture for IP core testing and debugging on network-on-chip, Proc. TENCON
Taji S, Karimi A, Ghadiry M, Fotovatikhah F (2015) An analytical approach to calculate power and delay of carbon-based links in on-chip networks. J Comput Theor Nanosci 12:1775–1779
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Fotovatikhah, F., Naraghi, B., Tavakoli, F. et al. A New Approach to Model the Effect of Topology on Testing Using Boundary Scan. J Electron Test 31, 301–310 (2015). https://doi.org/10.1007/s10836-015-5530-8
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DOI: https://doi.org/10.1007/s10836-015-5530-8