Abstract
Scan architecture is widely used method for testing of transition delay faults (TDF). Launch-on-capture (LOC) and Launch-on-shift (LOS) are methods in scan-based test. In scan-based test all the possible combinations of two pattern delay tests cannot be applied to the circuit under test due to the structural constraints of scan which results in poor test coverage. This problem is alleviated in enhanced scan method as it supports random test vectors for delay test vector pairs at the cost of significant area overhead. The area overhead for enhanced scan chain method can be reduced by replacing the redundant flip-flop with the hold latch in enhanced scan flip-flop. Hold latch based enhanced scan design needs a fast hold signal similar to scan-enable signal in LOS testing. Delay Testable Enhanced Scan Flip-Flop (DTESFF) implements the enhanced scan cell with the slow hold signal. In this work, DTESFF-based partial enhanced scan method is proposed for the reduction of test data volume. Simulation results on ISCAS ’89 benchmark circuit displays reduction of test data volume.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Patil, S., Savir, J.: Skewed-load transition test: part II, coverage. In: Proceedings of International Test Conference, p. 714 (1992)
Savir, J.: Skewed-load transition test: part I, calculus. In: Proceedings of International Test Conference, p. 705 (1992)
Savir, J., Patil, S.: On broad-side delay test. Very Large Scale Integr. (VLSI) Syst., 2, p. 368 (1994)
Xu, G., Singh, A.D.: Low cost launch-on-shift delay test with slow scan enable. In: Proceedings of European Test Symposium (2006)
Suhag, A.K., Ahlawat, S., Shrivastava, V. Choudhary, R.R.: Output gating performance overhead elimination for scan test. Int. J. Electron. 102(7), 1244–1252 (2015)
Suhag, A.K., Ahlawat, S., Shrivastava, V., Singh, N.: Elimination of output gating performance overhead for critical paths in scan test. Int. J. Circ. Archit. Des. 1(1), 62–73 (2013)
Ahlawat, S., Vaghani, D., Tudu, J., Suhag, A.: A cost effective technique for diagnosis of scan chain faults. In: Kaushik, B., Dasgupta, S., Singh, V. (eds.) VLSI Design and Test (VDAT 2017), Communications in Computer and Information Science, vol. 711, pp. 191–204. Springer, Singapore (2017)
Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Springer (2000)
Suhag, A.K., Shrivastava, V., Singh, N.: Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage. Int. J. Syst. Assur. Eng. Manag. 4(3), 303–311 (2013)
Suhag, A.K., Shrivastava, V.: Delay testable enhanced scan flip–flop: DFT for high fault coverage. In: Proceedings of International Symposium on Electronic System Design (ISED), pp: 129–133, (2011)
Suhag, A.K., Shrivastava, V.: Performance evaluation of delay testable enhanced scan flip–flop. Int. J. Syst. Assur. Eng. Manag. 3(3), 169–174 (2012)
Pei, S., Li, H., Li, X.: Flip-Flop selection for partial enhanced scan to reduce transition test data volume. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(12), 2157–2169 (2012)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Suhag, A.K. (2019). Reduction of Test Data Volume Using DTESFF-Based Partial Enhanced Scan Method. In: Yadav, N., Yadav, A., Bansal, J., Deep, K., Kim, J. (eds) Harmony Search and Nature Inspired Optimization Algorithms. Advances in Intelligent Systems and Computing, vol 741. Springer, Singapore. https://doi.org/10.1007/978-981-13-0761-4_50
Download citation
DOI: https://doi.org/10.1007/978-981-13-0761-4_50
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-0760-7
Online ISBN: 978-981-13-0761-4
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)