Utilizing On-chip Resources for Testing Embedded Mixed-signal Cores

Abstract

For mixed-signal cores on System-on-a-Chip (SoC) platforms, the current methodology in test development is to use special test modes for block isolation such that mixed-signal cores are accessible from the chip boundary through a well-defined interface. Since the access mechanism to the core is preserved, this method facilitates fast test development when the core is re-used on another SoC. In order to obtain the shortest per-device test times on low-cost test platforms, we explore the option of operating the SoC in its designed functional mode where all on-chip resources are fully available for test support. We demonstrate this new method for a microcontroller with embedded ADCs. For high-volume products, the ultimate target is to minimize test costs by maximizing the efficiency of testing multiple devices in parallel on one tester. We demonstrate two benefits of testing in a functional mode that increases parallel test efficiency: (1) Simultaneous testing of multiple on-chip cores, and (2) On-chip post-processing to reduce the amount of test data.