Abstract
This paper presents a 0.35-μm CMOS on-chip spectrum analyzer based on switched-capacitor (SC) techniques. The prototype device utilizes a 3-V supply and basically includes an SC sine-wave generator, a fourth-order high-selectivity SC filter, and a programmable gain amplifier followed by an 8-b analog-to-digital converter. A non-uniform sampling scheme, which adds one degree of freedom in determining the frequency response parameters of SC circuits, helps to obtain high programmability resolution without modifying any capacitor value. As a result, capacitor spread and total capacitor area are reduced as compared to traditional SC solutions and, hence, test area overhead is minimized. Experimental results demonstrate the effectiveness of the proposed approach to perform frequency response and total harmonic distortion measurements for frequencies up to 1 MHz.
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References
American Semiconductor Industry Association. International Technology Roadmap for Semiconductors: Test and Test Equipment, 2005 Edition.
J.L. Ausín, J.F. Duque-Carillo, G. Torelli, and E. Sánchez-Sinencio, “Switched-capacitor Circuits with Periodical Nonuniform Individual Sampling,” IEEE Trans. Circuits Syst.-II: Analog Digit. Signal Process., vol. 50, pp. 404-414, August 2003.
J.L. Ausín, J.F. Duque-Carrillo, G. Torelli, and J.V. Valverde, “Non-uniform Sampling SC Circuits Based on Noise-shaping Feedback Coding,” Proc. IEEE ISCAS vol. I, pp. 601-604, May 2003.
J.L. Ausín, G. Torelli, J.F. Duque-Carillo, and E. Sánchez-Sinencio, “Series/parallel Time-multiplexed Switched-capacitor Filters with Programmability Based on Non-uniform Sampling,” Analog Integr. Circuits Signal Process., vol. 46, pp. 241–252, March 2006.
R.P. Colbeck, “A CMOS Low-distortion Switched Capacitor Oscillator with Instantaneous Start-up,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 996-998, December 1984.
F. Dai, C. Stroud, D. Yang, and S. Qi, “Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer,” Proc. Int. Test Conference, Charlotte (North Carolina), pp. 271–280, October 2004.
P.E. Fleischer and K.R. Laker, “A Family of Active Switched-capacitor Biquad Building Blocks,” Bell Syst. Tech. J., vol. 58, pp. 2253–2269, October 1979.
P.E. Fleischer, A. Ganesan, and K.R. Laker, “A Switched Capacitor Oscillator with Precision Amplitude Control and Guaranteed Start-up,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 641–647, April 1985.
Q. Huang, “A Novel Technique for the Reduction of Capacitance Spread in High-Q SC Circuits,” IEEE Trans. Circuits Syst., vol. 36, pp. 121–126, January 1989.
G. Huertas, D. Vazquez, E.J. Peralías, A. Rueda, and J.L. Huertas, “Testing Mixed-Signal Cores: A Practical Oscillation-based Test in an Analog Macrocell,” IEEE Des. Test Comput., vol. 19, pp. 73–82, December 2002.
J. Jiang and E.K.F. Lee, “A ROM-less Direct Digital Frequency Synthesizer Using Segmented Nonlinear Digital-to-analog Converter,” Proc. IEEE Custom Integrated Circuits Conference, San Diego (California), pp. 165–168, May 2001.
D.A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1997.
M.G. Méndez-Rivera, A. Valdes-Garcia, J. Silva-Martinez, and E. Sánchez-Sinencio, “An On-chip Spectrum Analyzer for Analog Built-in Testing,” J. Electronic Testing: Theory and Applications, vol. 21, pp. 205–219, June 2005.
L.S. Milor, “A Tutorial Introduction to Research on Analog and Mixed-signal Circuit Testing,” IEEE Trans. Circuits Syst.-II: Analog Digit. Signal Process., vol. 45, pp.1047–1389, October 1998.
S. Mir, M. Lubaszewski, V. Liberali, and B. Courtois, “Built-in Self-test Approaches for Analogue and Mixed-signal Integrated Circuits,” Proc. IEEE MWSCAS, 95, pp. 1145–1150, August 1995.
H. Nosaka, Y. Yamaguchi, A. Yamagishi, H. Fukuyama, and M. Muraguchi, “A Low-power Direct Digital Synthesizer Using a Self-adjusting Phase-interpolation Technique,” IEEE J. Solid-State Circuits, vol. 36, pp. 1281–1285, August 2001.
G.W. Roberts and B. Dufort, “Making Complex Mixed-signal Telecommunication Integrated Circuits Testable,” IEEE Commun. Mag., vol. 37, pp. 90–96, June 1999.
C. Stroud, J. Morton, A. Islam, and H. Alassaly, “A Mixed-signal Built-in Self-test Approach for Analog Circuits,” Proc. IEEE Southwest Symposium on Mixed-Signal Design, Las Vegas (Nevada), pp. 196–201, February 2003.
G.C. Temes, S. Shu, and R. Schreier, “Architectures for ΔΣ DACs,” in Delta-Sigma Data Converters: Theory, Design, and Simulation (Eds. S.R. Norsworthy, R. Schreier, and G.C. Temes). New York: IEEE Press, 1997.
S.K. Tewksbury and R.W. Hallock, “Oversampled, Linear Predictive and Noise-shaping Coders of Order N > 1,” New York: IEEE Trans. Circuits Syst., vol. CAS-25, pp. 436–447, July 1978.
M.F. Toner and G.W. Roberts, “On the Practical Implementation of Mixed Analog-digital BIST,” Proc. IEEE Custom Integrated Circuits Conference, California, pp. 525–528, May 1995.
M.F. Toner and G.W. Roberts, “A BIST Scheme for a SNR, Gain Tracking, and Frequency Response Test of a Sigma-delta ADC,” IEEE Trans. Circuits Syst.-II: Analog Digit. Signal Process., vol. 41, pp. 1–15, January 1995.
D. Yang, F. Dai, and C. Stroud, “Built-in-self Test for Automatic Analog Frequency Response Measurement,” Proc. IEEE ISCAS 2005, vol. 3, pp. 2208–2211, May 2005.
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Domínguez, M.A., Ausín, J.L., Duque-Carrillo, J.F. et al. A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing. J Electron Test 22, 437–448 (2006). https://doi.org/10.1007/s10836-006-9503-9
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DOI: https://doi.org/10.1007/s10836-006-9503-9