Abstract
A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm2. Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.
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This Project was supported in part by the National Natural Science Foundation of China (No. 41274047), Natural Science Foundation of Jiangsu Province (No. BK2012639), and in part by Natural Science Foundation of Suzhou city (No. SYG201135), Science and Technology Enterprises in Jiangsu Province Technology Innovation Fund (BC2012121), Changzhou Science and Technology Support (Industrial) Project (CE20120074).
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Zhou, Xf., Jiang, Jg., Liu, Jh. et al. High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters. Analog Integr Circ Sig Process 80, 565–575 (2014). https://doi.org/10.1007/s10470-014-0347-4
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DOI: https://doi.org/10.1007/s10470-014-0347-4