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High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters

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Abstract

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm2. Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.

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References

  1. Sun, Y. C. (2000). High-frequency integrated analogue filters. Iee Proceedings-Circuits Devices and Systems, 147(1), 1–2. doi:10.1049/ip-cds:20000312.

    Article  Google Scholar 

  2. Bo, X., Yan, S., & Sanchez-Sinencio, E. (2004). An RC time constant auto-tuning structure for high linearity continuous-time & Sigma;& Delta; modulators and active filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 51(11), 2179–2188. doi:10.1109/tcsi.2004.836852.

    Article  Google Scholar 

  3. Schaumann, R., & Tan, M. A. (1989). The problem of on-chip automatic tuning in continuous-time integrated filters. In IEEE international symposium on circuits and systems (Vol. 101, pp. 106–109), 8–11 May 1989. doi:10.1109/iscas.1989.100302.

  4. Chawla, R., Graham, D. W., Smith, P. D., & Hasler, P. (2005). A low-power, programmable bandpass filter section for higher-order filter-bank applications. In IEEE international symposium on circuits and systems (ISCAS 2005) (Vol. 1983, pp. 1980–1983), 23–26 May 2005. doi:10.1109/iscas.2005.1465003.

  5. Banu, M., & Tsividis, Y. (1985). An elliptic continuous-time CMOS filter with on-chip automatic tuning. IEEE Journal of Solid-State Circuits, 20(6), 1114–1121. doi:10.1109/jssc.1985.1052448.

    Article  Google Scholar 

  6. Cherry, J. A., & Snelgrove, W. M. (1995). Analog filter banks with low intermodulation distortion. In 1995 IEEE international symposium on circuits and systems (ISCAS ‘95) (Vol. 2, pp. 1195–1198), 30 Apr–3 May 1995. doi:10.1109/iscas.1995.520358.

  7. Choi, Y. W., & Luong, H. C. (2001). A high-Q and wide-dynamic-range 70 MHz CMOS bandpass filter for wireless receivers. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48(5), 433–440. doi:10.1109/82.938553.

    Article  Google Scholar 

  8. Khorramabadi, H., & Gray, P. R. (1984). High-frequency CMOS continuous-time filters. IEEE Journal of Solid-State Circuits, 19(6), 939–948. doi:10.1109/jssc.1984.1052249.

    Article  Google Scholar 

  9. Otin, A., Celma, S., & Aldea, C. (2009). Continuous-time filter featuring Q and frequency on-chip automatic tuning. International Journal of Circuit Theory and Applications, 37(2), 221–242.

    Article  Google Scholar 

  10. Pai, P. K. D., Brewster, A. D., & Abidi, A. A. (1996). A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels. IEEE Journal of Solid-State Circuits, 31(11), 1803–1816. doi:10.1109/jssc.1996.542406.

    Article  Google Scholar 

  11. Silva-Martinez, J., Adut, J., Rocha-Perez, J. M., Robinson, M., & Rokhsaz, S. (2003). A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system. IEEE Journal of Solid-State Circuits, 38(2), 216–225. doi:10.1109/jssc.2002.807402.

    Article  Google Scholar 

  12. Silva-Martinez, J., Steyaert, M. S. J., & Sansen, W. (1992). A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning. IEEE Journal of Solid-State Circuits, 27(12), 1843–1853. doi:10.1109/4.173114.

    Article  Google Scholar 

  13. Tsividis, Y., Banu, M., & Khoury, J. (1986). Continuous-time MOSFET-C filters in VLSI. IEEE Journal of Solid-State Circuits, 21(1), 15–30. doi:10.1109/jssc.1986.1052478.

    Article  Google Scholar 

  14. Wegerif, S., & Redman-White, W. (1993). An integrated CMOS image-rejection mixer system for low-jitter secondary frequency references. In 1993 IEEE international symposium on circuits and systems (ISCAS ‘93) (Vol. 1012, pp. 1010–1013), 3–6 May 1993. doi:10.1109/iscas.1993.393895.

  15. Durham, A. M., Hughes, J. B., & Redman-White, W. (1992). Circuit architectures for high linearity monolithic continuous-time filtering. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 39(9), 651–657. doi:10.1109/82.193320.

    Article  MATH  Google Scholar 

  16. Lopez-Martinez, A., Antonio-Chavez, R., & Silva-Martinez, J. (2001). A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter with automatic tuning system. In The 2001 IEEE international symposium on circuits and systems (ISCAS 2001) (Vol. 1, pp. 156–159), 6–9 May 2001. doi:10.1109/iscas2001.921814.

  17. Mingdeng, C., Silva-Martinez, J., Rokhsaz, S., & Robinson, M. (2002). A 1.8 V CMOS, 80–200 MHz continuous-time 4th order 0.05°; equiripple linear phase filter with automatic tuning system. In IEEE international symposium on circuits and systems (ISCAS 2002) , 2002 (Vol. 5, pp. V-173–V-176).. doi:10.1109/iscas.2002.1010668.

  18. Hengsheng, L., & Karsilayan, A. I. (2001). A high frequency bandpass continuous-time filter with automatic frequency and Q-factor tuning. In The 2001 IEEE international symposium on circuits and systems (ISCAS 2001) (Vol. 1, pp. 328–331), 6–9 May 2001. doi:10.1109/iscas.2001.921859.

  19. Jaeyoung, S., Sunki, M., Soosun, K., Joongho, C., Soohyoung, L., Hojin, P., et al. (2003) 3.3-V baseband Gm-C filters for wireless transceiver applications. In Proceedings of the 2003 international symposium on circuits and systems (ISCAS ‘03) (Vol. 1, pp. I-457–I-460), 25–28 May 2003. doi:10.1109/iscas.2003.1205599.

  20. Khoury, J. M. (1991). Design of a 15-MHz CMOS continuous-time filter with on-chip tuning. IEEE Journal of Solid-State Circuits, 26(12), 1988–1997. doi:10.1109/4.104193.

    Article  Google Scholar 

  21. Krummenacher, F., & Joehl, N. (1988). A 4-MHz CMOS continuous-time filter with on-chip automatic tuning. IEEE Journal of Solid-State Circuits, 23(3), 750–758. doi:10.1109/4.315.

    Article  Google Scholar 

  22. Osa, J. I., Carlosena, A., & Lopez-Martin, A. J. (2001). MOSFET-C filter with on-chip tuning and wide programming range. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48(10), 944–951. doi:10.1109/82.974783.

    Article  Google Scholar 

  23. Viswanathan, T. R., Murtuza, S., Syed, V. H., Berry, J., & Staszel, M. (1982). Switched-capacitor frequency control loop [digital transducer]. IEEE Journal of Solid-State Circuits, 17(4), 775–778. doi:10.1109/jssc.1982.1051811.

    Article  Google Scholar 

  24. Raisanen-Ruotsalainen, E., Lasanen, K., Sijander, M., & Kostamovaara, J. (2002). A low-power 5.4 kHz CMOS gm-C bandpass filter with on-chip center frequency tuning. In IEEE international symposium on circuits and systems (ISCAS 2002), 2002 (Vol. 4, pp. IV-651–IV-654). doi:10.1109/iscas.2002.1010540.

  25. Karsilayan, A. I., & Schaumann, R. (2000). Mixed-mode automatic tuning scheme for high-Q continuous-time filters. IEEE Proceedings on Circuits, Devices and Systems., 147(1), 57–64. doi:10.1049/ip-cds:20000054.

    Article  Google Scholar 

  26. Rabaey, J. M. (2003). Digital integrated circuits (2nd ed.). Upper Saddle River: Prentice Hall.

    Google Scholar 

  27. Teo, T. H., Ee-Sze, K., & Uday, D. (2003). Gm-C complex transitional filter for low-IF wireless LAN application. In Proceedings of the 15th international conference on microelectronics (ICM 2003) (pp. 110–113), 9–11 Dec 2003. doi:10.1109/ICM.2003.1287734.

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Acknowledgments

This Project was supported in part by the National Natural Science Foundation of China (No. 41274047), Natural Science Foundation of Jiangsu Province (No. BK2012639), and in part by Natural Science Foundation of Suzhou city (No. SYG201135), Science and Technology Enterprises in Jiangsu Province Technology Innovation Fund (BC2012121), Changzhou Science and Technology Support (Industrial) Project (CE20120074).

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Correspondence to Jin-guang Jiang.

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Zhou, Xf., Jiang, Jg., Liu, Jh. et al. High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters. Analog Integr Circ Sig Process 80, 565–575 (2014). https://doi.org/10.1007/s10470-014-0347-4

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  • DOI: https://doi.org/10.1007/s10470-014-0347-4

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