Ultra-wide Bandwidth Inter-Chip Interconnects for Heterogeneous Millimeter-Wave and THz Circuits

The chip-to-chip interconnects are based on coplanar on-chip waveguides that connect edge-to-edge between chips. Figure 1 shows a top view and schematic cross section of the interconnects, as well as a perspective view. Based on the “Quilt Packaging” approach, the interconnects consist of metallic nodules inlaid along the edge of each die that are connected to conventional first-layer metallization on each chip. The chips are placed adjacent to each other on a carrier and soldered together along the edges to form a continuous coplanar waveguide between chips. Thus, this technique provides a means to form a system-in-package consisting of multiple die fabricated in disparate and potentially incompatible process flows.

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Fabrication processes for high-resistivity Si [9] and semi-insulating GaAs [10] die have been reported previously; the key steps are the formation of the inlaid nodules (using inductively coupled reactive ion etching (ICP-RIE), plating, and chemical–mechanical polishing), the formation of partial-thickness die separation streets using ICP-RIE (for the die reported here, the separation etch was ∼150 μm deep, while the wafer thickness was 500 μm), and thinning of the die using backside grinding to a final thickness of 100 μm. This final thinning step also singulates the die. For the structures reported here, the soldering was performed by using solder paste (Kester R276), applied to the nodules using pin transfer, followed by a reflow step at 270 °C for 30 s in laboratory air using commercial die-attach equipment. The fabrication and assembly is based on well-established processes that provide the potential for high throughput and fully automated assembly.

Interconnects with the dimensions described above were fabricated, and also simulated numerically using Ansys HFSS [10]. Figure 2 shows the measured and simulated insertion loss and return loss for these structures. Measurements were made using on-wafer probing from 0.1 to 110 GHz, and from 140 to 220 GHz in two bands. To suppress higher-order modes in the launcher structures, the chips were placed on carbon-impregnated microwave absorbers on the chuck of a probe station. One hundred-micrometer pitch ground-signal-ground Cascade Infinity on-wafer probes were used for the measurements. To improve measurement and calibration repeatability, the probe station was equipped with high-resolution (1-μm resolution, 3-μm accuracy) digital run-out gauges on the probe positioners for both vertical and lateral travel. This allows the operator to accurately set both the relative probe-to-probe spacing as well as the over-travel during probing. A two-tier calibration was used, with off-wafer impedance standards used for the first tier, followed by on-chip through-reflect-line (TRL) calibration in the second tier to set the s-parameter reference planes at the junction between the nodules and the launchers, as shown schematically in Fig. 1. The on-chip calibration standards (offset opens, through and delay lines) were fabricated simultaneously and in the same process flow with the launchers and interconnects. For the HFSS simulations, the interconnect structures (including the launchers) were simulated, along with the on-chip calibration structures; these simulation results were then post-processed using the TRL calibration algorithm so that the reference planes in the measurements are identical to those in the simulations. In the HFSS simulations, loss in the dielectric substrates (GaAs and Si) was included, as were conductive losses in the metallization (Ti/Au, 0.4 μm thick) and radiative losses. For consistency with the experimental configuration, the simulations also included a 3-mm-thick carbon-impregnated AlN absorber underneath the chips (modeled as a dielectric constant of 9 and loss tangent of 0.3).

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As can be seen in Fig. 2, a measured insertion loss of less than 0.8 dB from 0.1 to 220 GHz has been obtained, with a measured return loss greater than 11.5 dB over the full frequency range. The measured insertion loss tracks the simulation projections closely, with no more 0.2-dB deviation over the full frequency range. Likewise, the return loss also agrees well, with the most significant deviation being approximately 0.75–2-dB lower return loss at G band from the measurements than that predicted by simulation. The roughly sinusoidal deviation between the measured and simulated insertion loss at G band (140–220 GHz) is attributable to minor imperfections in the second-tier on-wafer calibration. To be conservative, we quote here the highest measured insertion loss. Simulation suggests that an insertion loss of 0.53 dB at 220 GHz should be expected if the calibration artifacts are eliminated. For frequencies up to 110 GHz, worst-case insertion loss is 0.25 dB (at 87.5 GHz in Fig. 2), with a return loss better than 16 dB. These measured results compare favorably with other integration approaches, including flip-chip integration and split-block waveguide-MMIC transitions. Flip-chip integration has been demonstrated with insertion loss of 0.6 dB to 100 GHz at 15-dB return loss (see e.g., [11]), but typically requires high-impedance compensation sections that increase area and reduce bandwidth [12]. For split-block waveguide transitions, transition losses of approximately 1 dB have been achieved (see e.g., [13]), corresponding to a chip-to-chip loss of ∼2 dB and return losses of ∼10 dB. Waveguide approaches are limited to the bandwidth of the host waveguide. Recently, a J-band (220–260) transition exhibiting <1-dB insertion loss at 220 GHz and return loss exceeding 10 dB has also been reported, based on silicon micromachining processes and cavity-backed coplanar waveguides [14]. To the authors’ knowledge, the Quilt Packaging-based edge-interconnect structure reported here represents the lowest insertion loss at these millimeter-wave and sub-THz frequencies for heterogeneous chip-to-chip integration, while maintaining return losses above 10 dB, and offering ultra-wide bandwidths (from DC through millimeter-wave frequencies).

The latency and group delay of the interconnects were also assessed. Figure 3 shows the measured and simulated insertion phase delay for the GaAs-Si interconnects, along with best-fit lines to constant delay. As can be seen, the simulations indicate that an almost dispersionless delay of 0.62 ps matches the results well, while the measurements result in a slightly larger delay of approximately 0.69 ps. This 70-fs deviation may arise in part from the deviation in geometric parameter L_air between the simulations and the structure that was characterized experimentally. For the simulations, no solder was included between the nodules (they were assumed to abut directly), with a total L_air of 10 μm (note however that the total distance between s-parameter reference planes is appreciably larger than 10 μm, leading to the larger total delay). Experimentally, however, we routinely observe that solder penetrates between the nodules during reflow, resulting in a slightly increased L_air value due to the finite thickness of the solder. This solder thickness is typically on the order of 5 μm. We estimate that this effect likely accounts for around one quarter of the observed deviation in phase; the rest is believed to be due to imprecision in probe positioning during measurement. An error in probe position of 4 μm would be sufficient to induce this degree of phase discrepancy (due to the larger dielectric constant of the substrates compared to air); this level of error is consistent with our probe placement repeatability. The nearly linear-phase characteristics and extremely short latency (measured at <0.7 ps) suggest that these interconnects are promising for ultra-wide bandwidth interconnects with low distortion.

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