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OptiPlace: optimized placement solution for mixed-size designs

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Abstract

In this paper, an optimized placement approach has been presented for mixed-size designs. A novel initial placement approach is introduced to achieve routability-aware global placement using new routability-aware cell clustering, cluster positioning, cluster movement, and pin offset based cell spreading methods. The routability-aware cell clustering groups a set of cells to lookahead the circuit routability. A new cell spreading methodology is employed based on the pin offsets to keep control on total wirelength. A routability-aware legalization has been implemented using new circle rolling and block sliding techniques. Finally, a routability-aware detailed placement is used to refine the placement in order to yield an optimized placement in terms of wirelength and routability for mixed-size designs. The detailed placement implemented by novel congestion hot spot detection, congestion contributing cells identification, congestion contributing cell movement techniques. A routing-congestion reduction method is used in detailed placement phase to refine the placement solution to achieve better routability. Our proposed placer is experimentally tested on ICCAD 2012 contest benchmarks. The solution quality of this proposed approach achieves improvised results than the contemporary in terms of HPWL, scaled wirelength, and routability. It achieves 1.02% and 3.53% improvement in terms of HPWL and routing congestion over one of the recent placers Ripple 2.0.

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References

  1. Wang, L.-T., Chang, Y.-W., & Cheng, K.-T. (2011). Electronic design automation: Synthesis, verification and test. Amsterdam: Elsevier Science.

    Google Scholar 

  2. Kahng, B., Lienig, J., Markov, I. L., & Hu, J. (2011). VLSI physical design: From graph partitioning to timing closure. Berlin: Springer.

    Book  Google Scholar 

  3. Alpert, C., Li, Z., Nam, G.-J., Sze, C. N., Viswanathan, N., & Ward, S. I. (2012). Placement: Hot or not? In Proceedings of ICCAD, pp. 283–290.

  4. Lin, T., Chu, C., Shinnerl, J. R., Bustany, I., & Nedelchev, I. (2015). POLAR: A high performance mixed-size wirelength-driven placer with density constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(3), 447–459.

    Article  Google Scholar 

  5. Viswanathan, N., Alpert, C. J., Sze, C., Li, Z., Nam, G. J., & Roy, J. A. (2011). The ISPD-2011 Routability-driven placement contest and benchmark suite. In Proceedings of ISPD, pp. 141–146.

  6. Viswanathan, N., Alpert, C. J., Sze, C., Li, Z., & Wei, Y. (2012). The DAC 2012 Routability-driven placement contest and benchmark suite. In Proceedings of the DAC, pp. 774–782.

  7. Viswanathan, N., Alpert, C. J., Sze, C., Li, Z., & Wei, Y. (2012). The ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. In Proceedings of the ICCAD, pp. 345–348.

  8. Yutsis, V., Bustany, I. S., Chinnery, D., Shinnerl, J. R., & Liu, W.-H. (2014). ISPD 2014 benchmarks with sub-45nm technology rules for detailed routing-driven placement. In Proceedings of the ISPD, pp. 161–168.

  9. Lou, J., Krishnamoorthy, S., & Sheng, H. S. (2001). Estimating routing congestion using probabilistic analysis. In Proceedings of the ISPD, pp. 112–117.

  10. Kahng, A. B., & Xu, X. (2003). Accurate pseudo-constructive wirelength and congestion estimation, Proceedings of the 2003 international workshop on system-level interconnect prediction, ser. SLIP ’03. pp. 61–68. ACM.

  11. Westra, J., Bartels, C., & Groeneveld, P. (2004). “Probabilistic congestion prediction”, In Proceedings of the 2004 international symposium on physical design, ser. ISPD ’04. pp. 204–209. ACM.

  12. Sham, C.-w., & Young, E.F.Y. (2005). Congestion prediction in early stages, In Proceedings of the 2005 international workshop on system level interconnect prediction, ser. SLIP ’05. pp. 91–98. ACM.

  13. Spindler, P., & Johannes, F. M. (April 2007). Fast and accurate routing demand estimation for efficient routability-driven placement, In 2007 design, automation test in Europe conference exhibition, pp. 1–6.

  14. Cheng, C.-L. E. (1994). Risa: Accurate and efficient placement routability modeling, Proceedings of the 1994 IEEE/ACM international conference on computer-aided design, ser. ICCAD ’94. pp. 690–695. IEEE Computer Society Press.

  15. Hou, W., Yu, H., Hong, X., Cai, Y., Wu, W., Gu, J., & Kao, W. H. (2001). A new congestion-driven placement algorithm based on cell inflation, in proceedings of the 2001 asia and south pacific design automation conference, ser. ASP-DAC ’01. pp. 605–608. ACM.

  16. Yang, X., Kastner, R., Sarrafzadeh, M., & M. Sarrafzadeh, (2001). “Congestion reduction during placement based on integer programming”, In Proceedings of the 2001 IEEE/ACM international conference on computeraided design, ser. ICCAD ’01. pp. 573–576. IEEE Press.

  17. Pan, M., & Chu, C. (Nov 2006). Fastroute: A step to integrate global routing into placement, In 2006 IEEE/ACM international conference on computer aided design, pp. 464–471.

  18. Hu, J., Roy, J. A., Markov, I. L. (2010). Completing high-quality global routes, In Proceedings of the 19th international symposium on physical design, ser. ISPD ’10. pp. 35–41. ACM.

  19. Wen-Hao L., W.-C. K. Y.-L. L., & Dai, K.-R. (2012). Trnsltor, [Online]. Available: https://people.cs.nctu.edu.tw/whliu/NCTU-GR.htm.

  20. Liu, W. H., Kao, W. C., Li, Y. L., & Chao, K. Y. (2013). Nctu-gr 2.0: Multithreaded collisionaware global routing with bounded-length maze routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(5), 709–722.

    Article  Google Scholar 

  21. Pan, M., & Chu, C. (2007). IPR: An integrated placement and routing algorithm. In Proceedings of the DAC, pp. 59–62.

  22. Kim, M.-C., Hu, J., Lee, D.-J., & Markov, I. L. (2011). A simPLR method for routability-driven placement. In Proceedings of the ICCAD, pp. 67–73.

  23. He, X., Huang, T., Xiao, L., Tian, H., & Young, E. F. Y. (2013). Ripple: A robust and effective routability-driven placer. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(10), 1546–1556.

    Article  Google Scholar 

  24. Lin, T., & Chu, C. (2014). Polar 2.0: An effective routability-driven placer, In Proceedings of the DAC, pp. 1–6.

  25. He, X., Wang, Y., Guo, Y., & Young, E. F. Y. (2016). Ripple 2.0: Improved movement of cells in routability-driven placement. ACM Transactions on Design Automation of Electronic Systems, 22(1), 101–1026.

    Article  Google Scholar 

  26. Cheng, C., Kahng, A. B., Kang, I., & Wang, L. (2019). RePlAce: Advancing solution quality and routability validation in global placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(9), 1717–1730.

    Article  Google Scholar 

  27. Hu, J., Roy, J. A., & Markov, I. L. (2010). Completing high-quality global routes. In Proceedings of the ISPD, pp. 35–41.

  28. Liu, W.-H., Kao, W.-C., Li, Y.-L., & Chao, K.-Y. (2010). Multi-threaded collision-aware global routing with bounded-length maze routing. In Proceedings of the DAC

  29. Roy, J. A., & Markov, I. L. (2007). Seeing the forest and the trees: Steiner wirelength optimization in placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(4), 632–644.

    Article  Google Scholar 

  30. Li, C., Xie, M., Koh, C.-K., Cong, J., & Madden, P. H. (2004). Routability driven placement and white space allocation. In Proceedings of the ICCAD, pp. 394–401.

  31. Tsota, K., Koh, C.-K., & Balakrishnan, V. (Nov 2008). “Guiding global placement with wire density”, In 2008 IEEE/ACM international conference on computer-aided design, pp. 212–217.

  32. Kahng, A. B., & Wang, Q. (2005). Implementation and extensibility of an analytic placer. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(5), 734–747.

    Article  Google Scholar 

  33. Jiang, Z.-W., Su, B.-Y., & Chang, Y.-W. (2008). Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. In Proceedings of the DAC, pp. 167–172.

  34. Chuang, Y. L., Nam, G. J., Alpert, C. J., Chang, Y. W., Roy, J., & Viswanathan, N. (2010). Design-hierarchy aware mixed-size placement for routability optimization. In Proceedings of the ICCAD, pp. 663–668.

  35. Hu, J., Kim, M. C., & Markov, I. L. (2013). Taming the complexity of coordinated place and route. In Proceedings of the DAC, pp. 1–7.

  36. Yang, X., Choi, B.-K., & Sarrafzadeh, M. (2003). Routability-driven white space allocation for fixed-die standard-cell placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(4), 410–419.

    Article  Google Scholar 

  37. Brenner, U., & Rohe, A. (2003). An effective congestion-driven placement framework. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(4), 387–394.

    Article  Google Scholar 

  38. Roy, J. A., Viswanathan, N., Nam, G. J., Alpert, C. J., & Markov, I. L. (Nov 2009). Crisp: Congestion reduction by iterated spreading during placement, In 2009 IEEE/ACM international conference on computer-aided design - digest of technical papers. pp. 357–362

  39. Hsu, M. K., Chen, Y. F., Huang, C. C., Chou, S., Lin, T. H., Chen, T. C., & Chang, Y. W. (2014). Ntuplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(12), 1914–1927.

    Article  Google Scholar 

  40. Kim, M.-C., Lee, D., & Markov, I. L. (2012). SimPL: An effective placement algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(1), 50–60.

    Article  Google Scholar 

  41. Kim, M.-C., & Markov, I. L. (2012). ComPLx: A competitive primal-dual Lagrange optimization for global placement. In Proceedings of the DAC, pp. 747–752.

  42. Kim, M.-C., Viswanathan, N., Alpert, C. J., Markov, I. L., & Ramji, S. (2012). MAPLE: Multilevel adaptive placement for mixed-size designs. Proc. ISPD, 193–200.

  43. Nam, G.-J., Reda, S., Alpert, C. J., Villarrubia, P. G., & Kahng, A. B. (2006). A fast hierarchical quadratic placement algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(4), 678–691.

    Article  Google Scholar 

  44. Viswanathan, N., Pan, M., & Chu, C. (2007). FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control, In Proceedngs of the ASP-DAC, Yokohama, Japan, pp. 135–140.

  45. Karimpour, N., Bustany, I., Kennings, A., & Behjat, L. (2017). A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement. Proc. ISPD, 141–148.

  46. Karimpour, N., Bustany, I., Kennings, A., Westwick, D., & Behjat, L. (May 2018). Eh?Legalizer: A high-performance standard-cell legalizer observing technology constraints. In ACM Transactions on Design Automation of Electronic Systems,23(4).

  47. Cong, J., Luo, G., Tsota, K., & Xiao, B. (2013). Optimizing routability in large-scale mixed-size placement. In Proceedings of the ASP-DAC, pp. 441–446.

  48. Datta, P., & Mukherjee, S. (2019). Architecture-aware routability-driven placer for large-scale mixed-size designs. IET Circuits, Devices and Systems, 13(8), 1209–1220.

    Article  Google Scholar 

  49. Darav, N. K., Kennings, A., Tabrizi, A. F., Westwick, D., & Behjat, L. (2016). Eh?Placer: A high-performance modern technology-driven placer. ACM Transactions on DAES, 21(3), 37.

    Google Scholar 

  50. Huang, C.-C., Chiou, C.-H., Tseng, K.-H., & Chang, Y.-W. (2015). Detailed-Routing-Driven Analytical Standard-Cell Placement. Proc. ASP-DAC, 378–383.

  51. Hsu, M.-K., Chou, S., Lin, T.-H., & Chang, Y.-W. (2011). Routability-driven analytical placement for mixed-size circuit designs. In Proceedings of the ICCAD, pp. 80–84.

  52. Zhang, Y., & Chu, C. (Nov 2009). Crop: Fast and effective congestion refinement of placement, In 2009 IEEE/ACM international conference on computer-aided design - digest of technical papers, pp. 344–350.

  53. Liu, W.-H., Koh, C.-K., & Li, Y.-L. (2013). Optimization of placement solutions for routability, In Proceedings of the DAC, pp. 153:1–153:9.

  54. Bustany, I. S., Chinnery, D., Shinnerl, J. R., & Yutsis, V. (2015). ISPD 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement. In Proceedings of the ISPD, pp. 157–164.

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Correspondence to Prasun Datta.

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Datta, P., Mukherjee, S. OptiPlace: optimized placement solution for mixed-size designs. Analog Integr Circ Sig Process 109, 501–515 (2021). https://doi.org/10.1007/s10470-021-01864-5

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