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Analysis of power for double-tail current dynamic latch comparator

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Abstract

The necessity of low-power, high-speed, and area proficient data converters makes dynamic cross-coupled latch based comparator more suitable for power efficiency and to maximize speed. In this paper, an investigation on the power of dynamic comparator is presented and the analytical expressions are derived. Since the dynamic comparator is a linear periodically time-variant system, use of a classical current model of CMOS with the assumption that the transistor remains in saturation is not valid for analysis. Here, the analytical expression of power is derived using the current model of CMOS, which is valid in all operational regions of the transistor. With the help of these analytical expressions, designers can obtain an intuition about the main contributors to the power consumption and fully explore the trade-off in terms of performance parameters such as speed, power, and power delay product (PDP). The circuit is designed and simulated in GPDK 90 nm CMOS technology. The circuit design is optimized for performance parameters using both, analytical expressions and parametric variation simulations. Post-layout simulations are also carried out for the design. The results confirm a significant reduction in the performance parameters. The maximum frequency can be increased up to 4.2 GHz at a supply of 1 V, at the power of 33 μW, delay of 51.76 ps, and has a layout size of 7.2 μm × 8.1 μm. The results verify the effectiveness of the presented analysis.

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  1. Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India

    Vijay Savani & N. M. Devashrayee

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Savani, V., Devashrayee, N.M. Analysis of power for double-tail current dynamic latch comparator. Analog Integr Circ Sig Process 100, 345–355 (2019). https://doi.org/10.1007/s10470-019-01472-4

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