Skip to main content
SpringerLink
Log in

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design. Oxford: Oxford University Press.

    Google Scholar 

  2. Baker, R. J., Li, H. W., & Boyce, D. E. (2005). CMOS: Circuit design, layout, and simulation. New York: IEEE press; Wiley-Interscience.

    Google Scholar 

  3. Carusone, T. C., Johns, D. A., & Martin, K. W. (2011). Analog integrated circuit design. New York: John Wiley & Sons.

    Google Scholar 

  4. Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Cheung, T.-S., Ogawa, J., et al. (2005). A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE Journal of Solid-State Circuits, 40, 1680–1687. doi:10.1109/JSSC.2005.852014.

    Article  Google Scholar 

  5. Maymandi-Nejad, M., & Sachdev, M. (2003). 1-bit quantizer with rail to rail input range for sub-1 V Sigma-Delta modulators. Electronics Letters, 39, 894–895. doi:10.1049/el:20030588.

    Article  Google Scholar 

  6. Blalock, B. J., Li, H. W., Allen, P. E., & Jackson, S. A. (2000). Body-driving as a low-voltage analog design technique for CMOS technology. In 2000 southwest symposium on mixed-signal design (Cat. No.00EX390) (pp. 113–118). doi: 10.1109/SSMSD.2000.836457.

  7. Mesgarani, A., Alam, M. N., Nelson, F. Z., & Ay, S. U. (2010). Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS. In 2010 53rd IEEE international midwest symposium on circuits and systems (pp. 893–896). doi: 10.1109/MWSCAS.2010.5548658.

  8. Ay, S. U. (2011). A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS. Analog Integrated Circuits and Signal Processing, 66, 213–221. doi:10.1007/s10470-010-9515-3.

    Article  Google Scholar 

  9. Uthaichana, P., & Leelarasmee, E. (2003). Low power CMOS dynamic latch comparators. In TENCON 2003. Conference on convergent technologies for the Asia-Pacific Region (Vol. 2, pp. 605–608).

  10. Savani, V., & Devashrayee, N. M. (2014). Performance analysis and characterization of shared charge and clocked-latch based comparator using 90-nm technology. Journal of VLSI Design Tools & Technology, 4, 20–26.

    Google Scholar 

  11. Savani, V., & Devashrayee, N. M. (2015). Analysis and characterization of dual tail current based dynamic latch comparator with modified SR latch using 90 nm technology. In 19th international symposium on VLSI design and test (VDAT), 2015 (pp. 1–2). doi: 10.1109/ISVDAT.2015.7208136.

  12. Savani, V., & Devashrayee, N. M. (2017). Implementation of low power rail-to-rail dynamic latch comparator with modified adaptive power control technique. Nirma University Journal of Engineering and Technology, 5, 1–7.

    Article  Google Scholar 

  13. Goll, B., & Zimmermann, H. (2009). A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Transactions on Circuits and Systems II: Express Briefs, 56, 810–814. doi:10.1109/TCSII.2009.2030357.

    Article  Google Scholar 

  14. Schinkel, D., Mensink, E., Klumperink, E., van Tuijl, E., & Nauta, B. (2007). A double-tail latch-type voltage sense amplifier with 18 ps setup + hold time. In 2007 IEEE international solid-state circuits conference. Digest of technical papers (pp. 314–605). doi: 10.1109/ISSCC.2007.373420.

  15. Schinkel, D., Mensink, E., Klumperink, E., van Tuijl, E., & Nauta, B. (2007). A low-offset double-tail latch-type voltage sense amplifier. In 2007 the annual workshop on circuits, systems, and signal processing.

  16. Babayan-Mashhadi, S., & Lotfi, R. (2014). Analysis and design of a low-voltage low-power double-tail comparator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22, 343–352. doi:10.1109/TVLSI.2013.2241799.

    Article  Google Scholar 

  17. Babayan-Mashhadi, S., & Sarvaghad-Moghaddam, M. (2014). Analysis and design of dynamic comparators in ultra-low supply voltages. In 2014 22nd Iranian conference on electrical engineering (ICEE) (pp. 255–258). doi: 10.1109/IranianCEE.2014.699954.

  18. Figueiredo, P. M., & Vital, J. C. (2006). Kickback noise reduction techniques for CMOS latched comparators. IEEE Transactions on Circuits and Systems II: Express Briefs, 53, 541–545. doi:10.1109/TCSII.2006.875308.

    Article  Google Scholar 

  19. Kim, J., Leibowitz, B. S., Ren, J., & Madden, C. J. (2009). Simulation and analysis of random decision errors in clocked comparators. IEEE Transactions on Circuits and Systems I: Regular Papers, 56, 1844–1857. doi:10.1109/TCSI.2009.2028449.

    Article  MathSciNet  Google Scholar 

  20. He, J., Zhan, S., Chen, D., & Geiger, R. L. (2009). Analyses of static and dynamic random offset voltages in dynamic comparators. IEEE Transactions on Circuits and Systems I: Regular Papers, 56, 911–919. doi:10.1109/TCSI.2009.2015207.

    MathSciNet  Google Scholar 

  21. Babayan-Mashhadi, S., & Lotfi, R. (2012). An offset cancellation technique for comparators using body-voltage trimming. Analog Integrated Circuits and Signal Processing, 73, 673–682. doi:10.1007/s10470-012-9925-5.

    Article  Google Scholar 

  22. Nikoozadeh, A., & Murmann, B. (2006). An analysis of latch comparator offset due to load capacitor mismatch. IEEE Transactions on Circuits and Systems II: Express Briefs, 53, 1398–1402. doi:10.1109/TCSII.2006.883204.

    Article  Google Scholar 

  23. Nuzzo, P., Bernardinis, F. D., Terreni, P., & der Plas, G. V. (2008). Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Transactions on Circuits and Systems I: Regular Papers, 55, 1441–1454. doi:10.1109/TCSI.2008.917991.

    Article  MathSciNet  Google Scholar 

  24. Wicht, B., Nirschl, T., & Schmitt-Landsiedel, D. (2004). Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuits, 39, 1148–1158. doi:10.1109/JSSC.2004.829399.

    Article  Google Scholar 

  25. Halim, I. S., Abidin, N. A., & Rahim, A. A. (2011). Low power CMOS charge sharing dynamic latch comparator using 0.18 μm technology. In 2011 IEEE regional symposium on micro and nano electronics (pp. 156–160). doi:10.1109/RSM.2011.6088314.

  26. Akbari, M., Maymandi-Nejad, M., & Mirbozorgi, S. A. (2013). A new rail-to-rail ultra low voltage high speed comparator. In 2013 21st Iranian conference on electrical engineering (ICEE) (pp. 1–6). doi: 10.1109/IranianCEE.2013.6599850.

  27. Kuo, B. J., Chen, B. W., & Tsai, C. M. (2015). A 0.6 V, 1.3 GHz dynamic comparator with cross-coupled latches. VLSI Design, Automation and Test. doi:10.1109/VLSI-DAT.2015.7114523.

    Google Scholar 

  28. Van Elzakker, M., van Tuijl, E., Geraedts, P., Schinkel, D., Klumperink, E., & Nauta, B. (2008). In A 1.9 μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC. In 2008 IEEE international solid-state circuits conference—digest of technical papers (pp. 244–610). doi: 10.1109/ISSCC.2008.4523148.

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India

    Vijay Savani & N. M. Devashrayee

Authors
  1. Vijay Savani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. N. M. Devashrayee
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vijay Savani.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Savani, V., Devashrayee, N.M. Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator. Analog Integr Circ Sig Process 93, 287–298 (2017). https://doi.org/10.1007/s10470-017-1040-1

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-017-1040-1

Keywords

Search

Navigation