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A calibration technique based on sub-stages’ weights of pipelined ADC

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Abstract

This paper describes an efficient background calibration technique for pipelined analog-to-digital converters (ADCs). This technique calibrate the interstage gain errors, capacitor mismatches and finite opamp open-loop gain by updating the weights of sub-stages that carry the information about these errors. A weight-based errors model is built to simplify calibration algorithm. The errors are merged into the weight of the corresponding stage. The first seven stages of every signal path are calibrated to achieve high resolution and eliminate errors. Two extra sub-stages are used in the calibration process to implement background calibration. The improved technique is used in a 14-bits 80 MS/s pipelined ADC. The results demonstrate that it can decrease errors, increase the effective number of bits by 2.04, and SFDR is 90.12 dB and ENOB is 13.2 bits. The ADC implemented in chartered 0.18 μm CMOS process consumes 260 mW, occupying a chip area of 7.16 mm2.

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Acknowledgments

This work was supported by the National High Technology Research and Development Program (“863” Program) of China (2015AA016901) and the Natural Science Foundation of Shanxi Province, China (Grant No. 2015011050).

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Authors and Affiliations

  1. College of Information Engineering, Taiyuan University of Technology, Taiyuan, 030024, China

    Huayu Jia & Yuxiang Lv

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  1. Huayu Jia
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  2. Yuxiang Lv
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Correspondence to Huayu Jia.

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Jia, H., Lv, Y. A calibration technique based on sub-stages’ weights of pipelined ADC. Analog Integr Circ Sig Process 89, 223–229 (2016). https://doi.org/10.1007/s10470-016-0818-x

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  • DOI: https://doi.org/10.1007/s10470-016-0818-x

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