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Digital calibration of pipelined ADC using Newton–Raphson algorithm

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Abstract

This paper presents a new digital background calibration method to correct MDAC errors. The novelty of this research is to use Newton–Raphson algorithm in order to reduce the number of divisions as well as power in digital domain. This is achieved by combining the conventional slope mismatch averaging and linear approximation technique to compute the correction coefficient in fast iterative method. To validate the accuracy of the proposed method, the digital part of the calibration scheme is implemented on FPGA. The superiorities of the proposed method are fast convergence time, less power consumption, and less digital complexity in compared to previous studies. These benefits are due to using split structure along with Newton–Raphson method. Several simulations of a 12-bit 100MS/s pipelined ADC indicate that SNDR/SFDR is improved from 30/33 dB to 70/79 dB after calibration. Calibration process is achieved in approximately 2000 clock cycles. The proposed ADC achieves a FoM of 0.03-pJ/conversion-step and consumes an analog power of 6.7 mW.

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Authors and Affiliations

  1. Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran

    Ehsan Zia, Ebrahim Farshidi & Abdolnabi Kosarian

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  1. Ehsan Zia
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  2. Ebrahim Farshidi
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  3. Abdolnabi Kosarian
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Correspondence to Ehsan Zia.

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Zia, E., Farshidi, E. & Kosarian, A. Digital calibration of pipelined ADC using Newton–Raphson algorithm. Analog Integr Circ Sig Process 104, 61–70 (2020). https://doi.org/10.1007/s10470-020-01659-0

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  • DOI: https://doi.org/10.1007/s10470-020-01659-0

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