Abstract
This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC’s specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This circuit is designed in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR at 2.112 GHz sampling rate with 36 mW power consumption and the effective figure of merit value is 0.24 pJ/step.
Similar content being viewed by others
References
Yao, Q., Wang, F.-Y., Gao, H., Wang, K., & Zhao, H. (2007). Location estimation in ZigBee Network based on fingerprinting. In Vehicular electronics and safety. ICVES. IEEE International Conference on, December 2007, pp. 1–6.
Terada, T., Fujiwara, R., Ono, G., Norimatsu, T., Nakagawa, T., Miyazaki, M., Suzuki, K., Yano, K., Maeki, A., Ogata, Y., Kobayashi, S., Koshizuka, N., & Sakamura, K. (2009). Intermittent operation control scheme for reducing power consumption of UWB-IR receiver. IEEE Journal of Solid-State Circuits, 44(10), 2702–2710.
Zhang, F., Jha, A., Gharpurey, R., & Kinget, P. (2009). An agile, ultra-wideband pulse radio transceiver With discrete-time wideband-IF. IEEE Journal of Solid-State Circuits, 44(5), 1336–1351.
Iida, S., Tanaka, K., Suzuki, H., Yoshikawa, N., Shoji, N., Griffiths, B., Mellor, D., Hayden, F., Butler, I., & Chatwin, J. (2005). A 3.1 to 5 GHz CMOS DSSS UWB transceiver for WPANs. In Solid-state circuits conference. Digest of Technical Papers. ISSCC. 2005 IEEE International Vol. 1, February 2005, pp. 214–594.
Thoppay, P. E., Dehollain, C., Green, M. M., & Declercq, M. J. (2011). A 0.24-nJ/bit super-regenerative pulsed UWB receiver in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 46(11), 2623–2634.
Yu, H., & Chang, M.-C. F. (2008). A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS. IEEE Transactions on Circuits and Systems II, 55(7), 668–672.
Lin, Y.-Z., Liu, Y.-T., & Chang, S.-J. (2007). A 5-bit 4.2-GS/s flash ADC in 0.13-um CMOS. In Custom Integrated Circuits Conference. CICC ’07. IEEE, September 2007, pp. 213–216.
Wang, S., & Hong, Z. (2010). Design of 4-bit parallel sub-sampling A/D converter for IR-UWB receiver. In Electronics, Circuits, and Systems (ICECS). 17th IEEE International Conference on, December 2010, pp. 1049–1052.
Klymenko, O., Fischer, G., & Martynenko, D. (2008). A high band non-coherent impulse radio UWB receiver. In Ultra-Wideband, 2008. ICUWB. IEEE International Conference on, September 2008, vol. 3, pp. 25–29.
Dehollain, C., Curty, J.-P., Declercq, M., & Joehl, N. (2008). Design and optimization of passive UHF RFID systems, Springer: New York.
Blazquez, R., Newaskar, P. P., Lee, F. S., & Chandrakasan, A. P. (2005). A baseband processor for impulse ultra-wideband communications. IEEE Journal of Solid-State Circuits, 40(9), 1821–1828.
Vaughan, R. G., Scott, N. L., & White, D. R. (1991). The theory of bandpass sampling. IEEE Transactions on Signal Processing, 39(9), 1973–1984.
Colli-Vignarelli, J., & Dehollain, C. (2011). A discrete-components impulse-radio ultrawide-band (IR-UWB) transmitter. IEEE Transactions on Microwave Theory and Techniques, 59(4), 1141–1146.
Qin, B., Wang, X., Xie, H., Lin, L., Tang, H., Wang, H., Chen, H., Zhao, B., Yang, L., & Zhou, Y. (2010). 1.8 pJ/Pulse programmable gaussian pulse generator for full-band noncarrier impulse-UWB transceivers in 90-nm CMOS. IEEE Transactions on Industrial Electronics, 57(5), 1555–1562.
El-Chammas, M., & Murmann, B. (2010). A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration. In VLSI Circuits (VLSIC), 2010 IEEE Symposium on, June 2010, pp. 157–158.
Wang, S., Maheshwari, V., & Serdijn, W. A. (2010). Instantaneously companding baseband SC low-pass filter and ADC for 802.1 la/g WLAN receiver. In Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 30 2010–June 2 2010, pp. 2215–2218.
El-Chammas, M., & Murmann, B. (2009). General analysis on the impact of phase-skew in time-interleaved ADCs. IEEE Transactions on Circuits and Systems I 56(5), 902–910.
Hwang, Y.-S., Huang, P.-H., Hwang, B.-H., & Chen, J.-J. (2009). An efficient power reduction technique for CMOS flash analog-to-digital converters. Analog Integrated Circuits and Signal Processing, 61, 271–278.
Sansen, W. (2006). Analog design essentials. Berlin: Springer.
Pelgrom, M. J. M., Duinmaijer, A. C. J., & Welbers, A. P. G. (1989). Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits, 24(5), 1433–1439.
Kattmann, K., & Barrow, J. (1991). A technique for reducing differential non-linearity errors in flash A/D converters. In Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International, February 1991, pp. 170–171.
Bult, K., & Buchwald, A. (1997). An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2. IEEE Journal of Solid-State Circuits, 32(12), 1887–1895.
Ito, T., & Itakura, T. (2010). A 3-GS/s 5-bit 36-mW flash ADC in 65-nm CMOS. In Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian, November 2010, pp. 1–4.
Figueiredo, P. M., & Vital, J. C. (2004). Averaging technique in flash analog-to-digital converters. IEEE Transactions on Circuits and Systems I, 51(2), 233–253.
Wang, S., Dehollain C., Hong, Z. (2012). A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter. Analog Integrated Circuits and Signal Processing, 72, 251–257.
Pan, H., & Abidi, A. A. (2003). Spatial filtering in flash A/D converters. IEEE Transactions on Circuits and Systems II, 50(8), 424–436.
Figueiredo, P. M., & Vital, J. C. (2006). Kickback noise reduction techniques for CMOS latched comparators. IEEE Transactions on Circuits and Systems II, 53(7), 541–545.
Miyahara, M., Matsuzawa, A. (2009). A low-offset latched comparator using zero-static power dynamic offset cancellation technique. In Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian, November 2009, pp. 233–236.
van der Wagt, J. P. A., Chu, G. G., & Conrad, C. L. (2004). A layout structure for matching many integrated resistors. IEEE Transactions on Circuits and Systems I, 51(1), 86–190.
Sundstrm, T., & Alvandpour, A. (2010). A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS. Analog Integrated Circuits and Signal Processing, 64, 215–222.
Lin, Y.-Z., Lin, C.-W., & Chang, S.-J. (2008). A 2-GS/s 6-bit flash ADC with offset calibration. In Solid-State Circuits Conference, 2008. A-SSCC ’08. IEEE Asian, November 2008, pp. 385–388.
Choi, M., Lee, J., Lee, J., & Son, H. (2008). A 6-bit 5-GSample/s Nyquist A/D converter in 65 nm CMOS. In VLSI Circuits, 2008 IEEE Symposium on, June 2008, pp. 16–17.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Wang, S., Dehollain, C. & Hong, Z. Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver. Analog Integr Circ Sig Process 74, 255–266 (2013). https://doi.org/10.1007/s10470-012-9966-9
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-012-9966-9