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A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

  • Mixed Signal Letter
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Abstract

Averaging network is adopted to reduce the front-end amplifier’s offset in the flash analog-to-digital converter (ADC) commonly at the cost of the boundary threshold error. Such error worsens the integral-nonlinearity and introduces distortion. An averaging termination scheme using intended asymmetric spatial filter response is proposed to overcome this problem. It matches the impulse response window width, W IR, to the active zero-crossing response window width, W ZX at the boundary of network. Analysis and simulation show that by tuning the ratio between termination resistor R T and averaging resistor R 1, the boundary error is reduced as close as to 1%. This method provides sufficient reliability since the resistance matching can be fabricated as high as 1% in modern CMOS technology. Its feasibility for the flash ADC has been validated by a 1GS/s 4-bit flash converter.

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Authors and Affiliations

  1. State Key Laboratory of ASIC & Systems, Fudan University, 201203, ShangHai, People’s Republic of China

    Shenjie Wang & Zhiliang Hong

  2. RFIC Lab, EPFL, Lausanne, Switzerland

    Catherine Dehollain

Authors
  1. Shenjie Wang
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  2. Catherine Dehollain
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  3. Zhiliang Hong
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Correspondence to Shenjie Wang.

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Wang, S., Dehollain, C. & Hong, Z. A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter. Analog Integr Circ Sig Process 72, 251–257 (2012). https://doi.org/10.1007/s10470-012-9832-9

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  • DOI: https://doi.org/10.1007/s10470-012-9832-9

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