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Improved analog and AC performance for high frequency linearity based applications using gate-stack dual metal (DM) nanowire (NW) FET (4H-SiC)

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A Correction to this article was published on 18 April 2024

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Abstract

In this manuscript, analog/RF performance, linearity, harmonic distortion, small signal AC performance and scattering parameter (S-parameters) metrics of gate-stack DM nanowire (NW) FET (4H-silicon carbide) have been critically examined with nanowire field effect transistor (NW FET) (silicon), nanowire (NW) field effect transistor (FET) (silicon carbide) and dual metal (DM) nanowire field effect transistor (NW FET) (silicon carbide). For a fair comparison, electrical characteristics like the majority and minority charge carrier concentration, energy and velocity in ON-State (Vgs = Vds = 1.0 V) and OFF-State (Vgs = 0.0 V and Vds = 1.0 V) have been evaluated. This paper combines the advantages of dielectric material having gate-stack HfO2 (Hafnium oxide) with high-k and Al2O3 (aluminium oxide) to attain a superior Ion/Ioff ratio, intrinsic gain (gm/gd), GFP (gain frequency product), GBWP (gain bandwidth product), TFP (transconductance frequency product), GTFP (gain transconductance frequency product), early voltage (Vea), maximum frequency of oscillation (fmax), gm2, gm3 (higher-order transconductances), UPG (unilateral power gain), maximum transducer power gain and delay. To check the relevancy of the device for RFIC applications, linearity assessment is performed by evaluating its several figure of merits like VIP2, voltage interception points (VIP3), third-order intercept point (IIP3), 1-dB compression point, third-order intermodulation distortion (IMD3), HD2, HD3, harmonic distortions (THD) for all contemplated devices. Additionally, scattering parameters have been examined to affirm the small signal performance. This is being deduced further that our proposed device analysis exhibits improved electrical and linearity characteristics, and all of these factors contribute to its use in high-power and high-frequency implementation.

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Acknowledgements

Authors are grateful to the Director, Maharaja Agrasen Institute of Technology, for providing the necessary facilities to carry out this research work.

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  1. IGDTUW, Kashmere Gate, New Delhi, India

    Neeraj Neeraj, Shobha Sharma, Anubha Goel, Sonam Rewari & R. S. Gupta

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  1. Neeraj Neeraj
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  2. Shobha Sharma
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  3. Anubha Goel
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  5. R. S. Gupta
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Correspondence to Neeraj Neeraj.

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Appendix

Appendix

See Appendix Tables 4 and 5.

Table 4 Performance analysis for contemplated device design in terms of various parameters
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Table 5 Parameters of the devices being investigated for small signal performance
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Neeraj, N., Sharma, S., Goel, A. et al. Improved analog and AC performance for high frequency linearity based applications using gate-stack dual metal (DM) nanowire (NW) FET (4H-SiC). Microsyst Technol 29, 1403–1416 (2023). https://doi.org/10.1007/s00542-023-05480-3

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