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Inherent limitations of hybrid transactional memory

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Abstract

Several hybrid transactional memory (HyTM) schemes have recently been proposed to complement the fast, but best-effort nature of hardware transactional memory with a slow, reliable software backup. However, the costs of providing concurrency between hardware and software transactions in HyTM are still not well understood. In this paper, we propose a general model for HyTM implementations, which captures the ability of hardware transactions to buffer memory accesses. The model allows us to formally quantify and analyze the amount of overhead (instrumentation) caused by the potential presence of software transactions. We prove that (1) it is impossible to build a strictly serializable HyTM implementation that has both uninstrumented reads and writes, even for very weak progress guarantees, and (2) the instrumentation cost incurred by a hardware transaction in any progressive opaque HyTM is linear in the size of the transaction’s data set. We further describe two implementations which exhibit optimal instrumentation costs for two different progress conditions. In sum, this paper proposes the first formal HyTM model and captures for the first time the trade-off between the degree of hardware-software TM concurrency and the amount of instrumentation overhead.

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Acknowledgements

The study was funded by Agence Nationale de la Recherche (Grant No. ANR-14-CE35-0010-01, project DISCMAT), National Science Foundation (Grant Nos. CCF-1217921, CCF-1301926), U.S. Department of Energy (Grant No. IIS-1447786).

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Authors and Affiliations

  1. Microsoft Research Cambridge, 21 Station Road, Cambridge, CB1 1BB, UK

    Dan Alistarh

  2. MIT Computer Science and Artificial Intelligence Laboratory, 77 Massachusetts Avenue, 32-G604, Cambridge, MA, 02139, USA

    Justin Kopinsky

  3. LTCI, Télécom ParisTech, Université Paris-Saclay, C213-2, 46 Rue Barrault, 75013, Paris, France

    Petr Kuznetsov

  4. Information Sciences Institute, University of Southern California, Room 1102, 4676 Admiralty Way, Marina del Rey, CA, 90292, USA

    Srivatsan Ravi

  5. MIT Computer Science and Artificial Intelligence Laboratory, 32 Vassar Street, 32-G622, Cambridge, MA, 02139, USA

    Nir Shavit

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  1. Dan Alistarh
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Correspondence to Srivatsan Ravi.

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An earlier version of this work appeared in the Proceedings of the 2015 International Symposium on Distributed Computing (DISC 2015) [5].

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Alistarh, D., Kopinsky, J., Kuznetsov, P. et al. Inherent limitations of hybrid transactional memory. Distrib. Comput. 31, 167–185 (2018). https://doi.org/10.1007/s00446-017-0305-3

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