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Realistic limits to computation

III. Climbing the third dimension

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Abstract

As far as ultra-dense crossbars are related to correspondingly dense wire arrays, the crossbar route to tera-scale integration depends on the availability of preparation techniques for wire arrays with density of 106 cm−1 or more. This linear density implies, for a planar arrangement, a pitch of 10 nm or less, which not only is at the limits of the current technical possibilities, but also can modify appreciably the band structure of silicon. A dramatic increase of density could only be achieved if it were possible to organize the nanowires in a three-dimensional fashion still exploiting the planar technology. In this work processes are described for the fabrication of out-of-plane, vertically arranged, polycrystalline silicon nanowires via a rigorously top-down batch process. These techniques are consistent with the production of wire arrays with linear density (projected on the surface) larger than that achievable with any other proposed top-down process. Used for the fabrication of the bottom wire arrays of crossbars, these processes should eventually allow a cross-point amount per unit area in excess of 1012 cm−2, thus providing candidate technologies for ultra tera scale integration. The technique developed for such out-of-plane crossbars can be used to implement new functions like coils, solenoids and transformers.

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Notes

  1. With GSI (giga-scale integration), TSI and so on, one intends the ability to integrate 109, 1012 etc. switching elements in the same chip. Generally, the chip area of complex circuits is slightly larger than 1 cm2, so that the above numbers are also a (slight) overestimate of the amount per square centimetre. Since the interest of this work is also addressed to the preparation of complex but small circuits (e.g. with total area of 102 μm2), I instead assume that acronyms GSI, TSI etc. denote the ability to batch fabricate at the density of 109, 1012 cm−2 etc. Unless otherwise specified, ‘density’ will henceforth be the short form of ‘areal density’.

  2. Without pretending to consider economic problems, I recall that the cost of an apparatus for deep-ultraviolet lithography is about 30 M$. The low throughput of electron-beam lithography is due to the fact that this technique defines the pattern in a serial way and the throughput varies with the feature size F roughly as F 4 [51].

  3. This estimate follows from assuming the whole mankind as potential consumer, that the swarm is formed by 105 agents and that they have a clearance time of 1 year [67].

  4. Actually also the CMOS technology is characterized, for the preparation of interconnects, by the repetition of the same process. However, although the complexity of an interconnection layer is presumably much lower than that of a crossbar, the CMOS technology has been involved in the reduction of the number of interconnecting layers via the use of insulators with lower dielectric constant than SiO2 and conductors with higher electrical conductivity than aluminium.

  5. The progress of electronics is paced not only by the continuous improvements of its basic technology (lithography) that have reduced the feature size from the submillimetre length scale to the deep- submicrometre one, but also (and at the beginning mainly) by the invention of techniques for the self-alignment of one layer with respect to another. Among them the most important ones are the spacer-patterning technique (for the self-alignment of contacts with respect to the gate), local oxidation of silicon (for the self-alignment of active zones with respect to the field) and silicon-gate technology (for the self-alignment of source and drain with respect to the gate).

    History is sparing of compliments to scientists, and even more to technologists: although everybody of the one hundred thousand researchers involved in silicon-device processing is familiar with the silicon-gate technology, the paper reporting its invention in 1968 [71] and the one describing its practical application one year later [72] have had, according to the Institute of Scientific Information, 112 and 42 quotations only [73].

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Cerofolini, G.F. Realistic limits to computation. Appl. Phys. A 106, 967–982 (2012). https://doi.org/10.1007/s00339-011-6724-2

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