Design, Implementation, and Evaluation of Stochastic FIR Filters Based on FPGA

Abstract

Multiply-and-Accumulate (MAC) unit is a key element in various applications of digital signal processing. Researchers have shown the MAC implemented in the domain of Stochastic Computing (SC), a computing diagram based on probability-encoded Stochastic Numbers (SN), presents appealing properties of low area, low power, and flexible precision compared to its counterpart in conventional binary-encoded approaches. However, existing designs of SC-MAC suffer from inherent random fluctuation noise of SN. To achieve satisfactory accuracy, a long SN must be generated and introduce large latency. In this paper, we propose an SC-MAC design that is optimized in signed operation and a linear phase FIR filter that benefits from SC. By exploiting the properties of Low-Discrepancy (LD) sequence, we halve the latency with less hardware consumption without losing accuracy. For filter design, we specifically choose the linear phase FIR filter that is not only a structure widely used but can match and benefit our optimized SC-MAC in terms of minimizing memory usage. Experimental results show that the proposed design outperforms state-of-the-art SC-based FIR filters in accuracy at the same sequence length. Furthermore, the proposed design achieves the least hardware consumption at the same accuracy on FPGA compared to the existing works.

Appendix A Van der Corput Sequence Fundamentals

A van der Corput (VDC) sequence is an example of the simplest low-discrepancy (LD) sequence over the unit interval. It was first described in 1935 by the Dutch mathematician J. G. van der Corput. It is constructed by reversing the binary representation of the sequence of nonnegative integers n,

$$\begin{aligned} n = \sum _{i = 0}^{B-1}{d_i[n] 2^{i-B}}, (n \in {\mathbb {N}}^+) \end{aligned}$$

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The $d_i[n]$ is the i-th digit of the B-bit binary representation of nonnegative integers n. The corresponding B-bit binary number in VDC sequence is,

$$\begin{aligned} g[n] = \sum _{i = 0}^{B-1}{d_i[n] 2^{-i-1}}, (n \in {\mathbb {N}}^+) \end{aligned}$$

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Finally, the generation of a VDC sequence in the hardware is achieved by reversing the order of a counter’s output.

Table 6 Example of VDC sequence and the stochastic number generation

In the SNG, we described in Sect. 2.1, the VDC sequence serves as one of the inputs of the WBG, which is essentially a priority encoder that selects the input binary digit. Which digit is selected is determined by the most significant one in VDC sequence g[n], in other words, the least significant one of the counter’s output n.

The least significant one of continuous nonnegative integers n follows a regular pattern that we exploited to optimize the SC-MAC. Let L[n] indicate the least significant one position of n. From Table 6, two properties of the stochastic number generated from the VDC sequence can be observed: All the odd elements of a VDC sequence are still a VDC sequence consisting of the remaining bits $(x_{B-2} x_{B-3}\ldots x_0)_{bin}$, and all the even elements of a VDC sequence are the MSB $x_B-1$. The detailed mathematical proof is provided below.

Theorem 1

$L[n] = k$, if $n = N \times 2^{k+1} + 2^k, (N, k \in {\mathbb {N}})$

Proof

If the position of the least significant one of a binary number is k (i.e., $L(n) = k$), then two conditions should be fulfilled:

• 1. The lower bits are all zeros.

• 2. The k-th bit is one.

The first condition indicates that

$$\begin{aligned} n = R \times 2^k , R \in {\mathbb {N}} \end{aligned}$$

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while the second condition requires that

$$\begin{aligned} R = 2 \times N + 1, N \in {\mathbb {N}} \end{aligned}$$

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Therefore, $n = N \times 2^{k+1} + 2^k$

$\square$

Corollary 1

$L[n] = L[m] + k$, if $n = m \times 2^{k}, (k \in {\mathbb {N}}, m \in {\mathbb {N}}^+)$

Proof

Per Theorem 1, assuming $L[m] = p, (p \in {\mathbb {N}}^+)$, we have

$$\begin{aligned} m = N \times 2^{p+1} + 2^p \end{aligned}$$

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Therefore,

$$\begin{aligned} n= & {} m \times 2^{k} = N \times 2^{k+p+1} + 2^{k+p} \end{aligned}$$

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$$\begin{aligned} L[n]= & {} p + k = L[m] + k \end{aligned}$$

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$\square$

Now we prove the two properties we described in Sec. 3.1. By substituting $k = 1$ into Corollary 1, and $k = 0$ into Theorem 1, we have

$$\begin{aligned} L[n] =\left\{ \begin{aligned} L[m] + 1,&{\text { if } n = m \times 2}\\ 0,&{\text { if }n = m \times 2 + 1}\\ \end{aligned} \right. \end{aligned}$$

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The two properties are explained.